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From: anton@mips.complang.tuwien.ac.at (Anton Ertl)
Newsgroups: comp.arch
Subject: Re: Byte Addressability And Beyond
Date: Thu, 30 May 2024 12:50:38 GMT
Organization: Institut fuer Computersprachen, Technische Universitaet Wien
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Lawrence D'Oliveiro <ldo@nz.invalid> writes:
>On Wed, 29 May 2024 07:04:35 GMT, Anton Ertl wrote:
>
>> Lawrence D'Oliveiro <ldo@nz.invalid> writes:
>>
>>>Isn’t the point of RISC that these complex operations are
>>>more efficiently performed by a sequence of simpler instructions?
>> 
>> The IBM z series are not RISCs.
>
>Doesn’t matter. The principles of designing high-performance architectures 
>still apply: simpler instructions are better than more complex ones.

Is IBM z a high-performance architecture?

In the present case, the principles of designing high-performance
architectures will tell you that you don't need these instructions.

But if we forget about that for a minute, the block-copy-style
approach of IBM's CU14 instruction means that it could use a stream
buffer internally to avoid the performance snag that I mentioned in
another posting.

However, there is a big difference between what performance features
one can imagine and what is actually implemented.  I think that's the
marketing attraction of providing some feature as an instruction: it
lets the sales victim's imagination do the marketing/selling.

Concerning reality: When I looked at block copying a while ago
(Skylake/Zen1 days), I found that my code using a loop of AVX moves
outperformed REP MOVSB (where Intel and AMD's microcode should have
done at least as well) in many cases, and that despite Intel adding
"fast string moves" in IIRC Sandy Bridge.

- anton
-- 
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>