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From: anton@mips.complang.tuwien.ac.at (Anton Ertl)
Newsgroups: comp.arch
Subject: Re: is Vax addressing sane today
Date: Sat, 05 Oct 2024 08:01:23 GMT
Organization: Institut fuer Computersprachen, Technische Universitaet Wien
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George Neuner <gneuner2@comcast.net> writes:
>On Fri, 04 Oct 2024 07:05:34 GMT, anton@mips.complang.tuwien.ac.at
>(Anton Ertl) wrote:
>
>>George Neuner <gneuner2@comcast.net> writes:
>>>You are, of course, aware that the complex "x86" instruction set is an
>>>illusion and that the hardware essentially has been a load-store RISC
>>>with a complex decoder on the front end since the Pentium Pro landed
>>>in 1995.
>>
>>Repeating nonsense does not make it any truer, and this nonsense has
>>been repeated since at least the Pentium Pro (1995), maybe already
>>since the 486 (1989).  CISC and RISC are about the instruction set,
>>not about the implementation.  And even if you look at the
>>implementation, it's not true: The P6 has microinstructions that are
>>~100 bits long, whereas RISCs have 32-bit and 16-bit instructions.
>>The K7 has load-store microinstructions; RISCs don't have that.
>
>Anton, you know very well that the hardware does not execute the "x86"
>instruction set but only /emulates/ it.  The decoder translates x86
>instructions into sequences of microinstructions that perform the
>equivalent operations.  The fact that some simple instructions
>translate one to one does not change this.

I know that the hardware does not execute the "x86" instruction set,
because there is no "x86" instruction set.  There is the 80286
instruction set, the IA-32 instruction set, and the AMD64 instruction
set (and the boundary between 286 and IA-32 is squishy, but that
between those and AMD64 is hard).

As for the point you are trying to make, I know quite a bit about how
the instruction execution is implemented on various IA-32 and AMD64
implementations.  Whether you call it execution or emulation, IA-32
and AMD64 are still the instruction sets of all of them, and there is
no way to execute (or emulate) other instruction sets, and no way to
run programs written in macro-ops, micro-ops, ROPs, or whatever they
may be called.  That's even true for the Transmeta implementations
(although doing other instruction sets would have been possible there
and IIRC was demonstrated once).  Moreover, these
implementation-specific things change from one implementation to the
next, and that includes the implementations by Transmeta.

For the 6502 or the MIPS R2000 we don't consider the instruction set
to be emulated, either, and they have a decoder that translates the
instructions into sequences of signals to various units (i.e.,
microinstructions), too.

- anton
-- 
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>