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Path: ...!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: anton@mips.complang.tuwien.ac.at (Anton Ertl) Newsgroups: comp.arch Subject: Re: is Vax addressing sane today Date: Sun, 06 Oct 2024 08:40:55 GMT Organization: Institut fuer Computersprachen, Technische Universitaet Wien Lines: 60 Message-ID: <2024Oct6.104055@mips.complang.tuwien.ac.at> References: <vdg3d1$2kdqr$1@dont-email.me> <memo.20241001101211.19028o@jgd.cix.co.uk> <20241001123426.000066c1@yahoo.com> <2024Oct1.182625@mips.complang.tuwien.ac.at> <vdknel$3e4pf$9@dont-email.me> <2024Oct3.085754@mips.complang.tuwien.ac.at> <vdne1a$3uaeh$4@dont-email.me> <m1rufjhpi09m9adedt87nrcdfmij1i8pvb@4ax.com> <2024Oct4.090534@mips.complang.tuwien.ac.at> <vdsnk4$ukl1$6@dont-email.me> Injection-Date: Sun, 06 Oct 2024 11:15:42 +0200 (CEST) Injection-Info: dont-email.me; posting-host="9f5fea38e9806ac24398be8213ac3035"; logging-data="1249592"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+Zklva9uUk1y4g9OEVXumc" Cancel-Lock: sha1:i6apr1wzPA6kq/mkmyItwDDGH08= X-newsreader: xrn 10.11 Bytes: 3809 Lawrence D'Oliveiro <ldo@nz.invalid> writes: >Intel I think tried to spread this idea of a "RISC core" somewhere inside >the labyrinthine complexity of its Pentium-and-later chips, in the hope >that some of the aura attached to the term "RISC" would rub off on its >products. I am not sure it was Intel, but certainly a number of people on the net did write this, and it may already have started with the 486, and my guess is that even an explanation of Intel that just expained the implementation of the 486 without making any claim that the 486 is a RISC would have led to that result. It's just a thing that people rooting for Intel like to believe, so in retelling the implementation explanation, they eventually settle down to "the 486 is a RISC internally", and eventually this becomes "the complex 'x86' instruction set is an illusion and that the hardware essentially has been a load-store RISC". AMD are easily provable culprits in this scam: They call their micro-ops "ROPs", for RISC ops. BTW, this page looks at the microcode of different IA-32 implementations: <https://fanael.github.io/is-x86-risc-internally.html> >And quite a few people fell for it. Yes. Apparently it's something people want to believe in. >> ... ARM A64 and RISC-V are clearly RISCs. > >ARM and some other RISC architectures (e.g. POWER) do somewhat stretch the >term though, don’t they, when they add that combinatorial explosion of >operand types in their short-vector instructions. Number of operand types never has been a criterion in any of the RISC definitions I have seen, nor the number of instructions (although some people like to go by that). As for ARM and Power, from <2024Jan12.145502@mips.complang.tuwien.ac.at>: CPU Age 3a 3b 3c 3d 4a4b 5a 5b 6a 6b# ODD (1991) RULE <6 =1 =4 <5 =0 =0=1 <2 =1 >4 >3 G1 1 1 4 4 0 0 1 1 1 5 5 - IBM RS/6000 6+ 1 4 7+ 0 0 1 0 1 4+ - 3/8 ARM1 -12 2+ 4 7+ 0 0 1 1 2+ 4+ 5 4/7 ARMv7 T32 -22 1 4 15+ 0 0 1 1 2+ 5 5 2/9 ARM A64 So for John Mashey the RS/6000 (original Power) satisfied all his RISC criteria. I think that since the PowerPC, Power fails his criteria 5b and maybe 5a, so these days Power would be classified as 1/10 or 2/9 (i.e., 10 for RISC, 1 against), so it's clearly RISC, like the others, and unlike AMD64 (7/4). - anton -- 'Anyone trying for "industrial quality" ISA should avoid undefined behavior.' Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>