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Path: ...!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: anton@mips.complang.tuwien.ac.at (Anton Ertl) Newsgroups: comp.arch Subject: Re: is Vax addressing sane today Date: Mon, 07 Oct 2024 17:09:10 GMT Organization: Institut fuer Computersprachen, Technische Universitaet Wien Lines: 37 Message-ID: <2024Oct7.190910@mips.complang.tuwien.ac.at> References: <vdg3d1$2kdqr$1@dont-email.me> <20241001123426.000066c1@yahoo.com> <2024Oct1.182625@mips.complang.tuwien.ac.at> <vdknel$3e4pf$9@dont-email.me> <2024Oct3.085754@mips.complang.tuwien.ac.at> <vdne1a$3uaeh$4@dont-email.me> <m1rufjhpi09m9adedt87nrcdfmij1i8pvb@4ax.com> <2024Oct4.090534@mips.complang.tuwien.ac.at> <vdsnk4$ukl1$6@dont-email.me> <2024Oct6.104055@mips.complang.tuwien.ac.at> <vdv6ta$1dc01$8@dont-email.me> <2024Oct7.091702@mips.complang.tuwien.ac.at> <20241007122709.000072c0@yahoo.com> Injection-Date: Mon, 07 Oct 2024 19:30:16 +0200 (CEST) Injection-Info: dont-email.me; posting-host="f074140e0322ced0afa14df7d2a88fd0"; logging-data="1888505"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/X1OgpZrStnM/10WYwvsjQ" Cancel-Lock: sha1:oEQ1Tol8tYxL+uqgjn2io+FMP14= X-newsreader: xrn 10.11 Bytes: 2723 Michael S <already5chosen@yahoo.com> writes: >On Mon, 07 Oct 2024 07:17:02 GMT >anton@mips.complang.tuwien.ac.at (Anton Ertl) wrote: > >> >> However, in John Mashey's criteria the number of registers plays a >> role; he requires >4 bits for the GPR specifier, and >3 bits for the >> FPR specifier. >> >> - anton > >Which sounds rather arbitrary. In a way it is, but see below. >Or even worse, like if he wanted for >SPARC to be called 'typical RISC' and for ARM to be called atypical and >had chosen the numbers to match the agenda. I think that ARM did not exist for John Mashey. He probably chose the criterion ">4 bits" because it excluded VAX. So, yes, his criteria were based on classifying some architectures as RISCs and some as CISCs, and then drawing the lines to fit that classification. But his criteria also work for architectures he did not look at, including ARM A32, even if not every criterion agrees with all the others for every architecture. Alternatively, you could do a cluster analysis with these criteria and maybe others, and I think that the RISCs would come out pretty tightly clustered; the non-RISCs would be further away from that, and I doubt that they would form a single cluster. - anton -- 'Anyone trying for "industrial quality" ISA should avoid undefined behavior.' Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>