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Path: ...!news.mixmin.net!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: anton@mips.complang.tuwien.ac.at (Anton Ertl) Newsgroups: comp.arch Subject: Re: is Vax addressing sane today Date: Tue, 10 Sep 2024 07:43:53 GMT Organization: Institut fuer Computersprachen, Technische Universitaet Wien Lines: 44 Message-ID: <2024Sep10.094353@mips.complang.tuwien.ac.at> References: <vbd6b9$g147$1@dont-email.me> <memo.20240905225550.19028d@jgd.cix.co.uk> <2024Sep6.080535@mips.complang.tuwien.ac.at> <vbiftm$ui9$1@gal.iecc.com> <2024Sep8.155511@mips.complang.tuwien.ac.at> <73c6d21457c487c61051ec52fe25ea5d@www.novabbs.org> <vbl3qj$22a2q$1@dont-email.me> <09ce1622b872f0b0fa944e868a8c97be@www.novabbs.org> <vbnisc$2hb59$1@dont-email.me> Injection-Date: Tue, 10 Sep 2024 10:04:58 +0200 (CEST) Injection-Info: dont-email.me; posting-host="f21f15281580639cd9bc25764f54f587"; logging-data="2997940"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+rgxJ+3yKUihBiLdPzuDiO" Cancel-Lock: sha1:AS2Dhl4+Uo9VsqSOpWloUMVuDxw= X-newsreader: xrn 10.11 Bytes: 3231 Brett <ggtgp@yahoo.com> writes: >Speaking of complex things, have you looked at Swift output, as it checks >all operations for overflow? > >You could add an exception type for that, saving huge numbers of correctly >predicted branch instructions. > >The future of programming languages is type safe with checks, you need to >get on that bandwagon early. MIPS got on that bandwagon early. It has, e.g., add (which traps on signed overflow) in addition to addu (which performs modulo arithmetic). It has been abandoned and replaced by RISC-V several years ago. Alpha got on that bandwagon early. It's a descendent of MIPS, but it renamed add into addv, and addu into add. It has been canceled around the year 2000. RISC-V, another descendent of MIPS, has an add instruction that corresponds to MIPS' addu, and no instruction that corresponds to MIPS' add. They obviously don't think that there's a bandwagon. Note that RISC-V was designed after Swift was introduced. IA-32 got on that bandwagon early. It has a single-byte instruction trapv that traps if the overflow flag is set. The AMD64 instruction set is very similar to the IA-32 instruction set, but one of the few differences is that the trapv instruction was eliminated, and the encoding replaced with a REX prefix. The AMD64 architects obviously don't think that there is a bandwagon. Apple has been designing their own silicon for a while, and they have introduced Swift as their language in 2010. Yet they have not switched to an architecture like MIPS or Alpha, nor have they designed their own architecture or architecture extension that includes instructions like Alpha's addv or IA-32's trapv. Instead, they switched to ARM A64, which does not have such features, after introducing Swift in 2010. They obviously don't think that there is such a bandwagon, either. - anton -- 'Anyone trying for "industrial quality" ISA should avoid undefined behavior.' Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>