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From: anton@mips.complang.tuwien.ac.at (Anton Ertl)
Newsgroups: comp.arch
Subject: Re: is Vax addressing sane today
Date: Sun, 22 Sep 2024 09:25:30 GMT
Organization: Institut fuer Computersprachen, Technische Universitaet Wien
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mitchalsup@aol.com (MitchAlsup1) writes:
>There is no microcode outside of Z-system these days.

Every AMD64 processor has microcode.  E.g., on an Alder Lake system
"perf list" lists the following events that have "microcode" in their
description:

  machine_clears.fp_assist
       [Counts the number of floating point operations retired that required
        microcode assist. Unit: cpu_atom]
  assists.fp
       [Counts all microcode FP assists. Unit: cpu_core]
  machine_clears.slow
       [Counts the number of machine clears that flush the pipeline and
        restart the machine with the use of microcode due to SMC,
        MEMORY_ORDERING, FP_ASSISTS, PAGE_FAULT, DISAMBIGUATION, and
        FPC_VIRTUAL_TRAP. Unit: cpu_atom]
  topdown_be_bound.serialization
       [Counts the number of issue slots every cycle that were not consumed by
        the backend due to scoreboards from the instruction queue (IQ), jump
        execution unit (JEU), or microcode sequencer (MS). Unit: cpu_atom]
  topdown_fe_bound.cisc
       [Counts the number of issue slots every cycle that were not delivered
        by the frontend due to the microcode sequencer (MS). Unit: cpu_atom]
  assists.any
       [Number of occurrences where a microcode assist is invoked by hardware.
        Unit: cpu_core]
  tma_microcode_sequencer
       [This metric represents fraction of slots the CPU was retiring uops
        fetched by the Microcode Sequencer (MS) unit. Unit: cpu_core]
  IpAssist
       [Instructions per a microcode Assist invocation. See Assists tree node
        for details (lower number means higher occurrence rate). Unit:
        cpu_core]
  tma_heavy_operations
       [This metric represents fraction of slots where the CPU was retiring
        heavy-weight operations -- instructions that require two or more uops
        or microcoded sequences. Unit: cpu_core]
  tma_cisc
       [Counts the number of issue slots that were not delivered by the
        frontend due to the microcode sequencer (MS). Unit: cpu_atom]
  tma_serialization
       [Counts the number of issue slots that were not consumed by the backend
        due to scoreboards from the instruction queue (IQ), jump execution
        unit (JEU), or microcode sequencer (MS). Unit: cpu_atom]
tma_microcode_sequencer_group:
  tma_assists
       [This metric estimates fraction of slots the CPU retired uops delivered
        by the Microcode_Sequencer as a result of Assists. Unit: cpu_core]

tma_microcode_sequencer, IpAssist, tma_heavy_operations, tma_cisc
occurs several times in different sections.

- anton
-- 
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>