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Path: ...!3.eu.feeder.erje.net!feeder.erje.net!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: anton@mips.complang.tuwien.ac.at (Anton Ertl) Newsgroups: comp.arch Subject: Re: is Vax addressing sane today Date: Mon, 09 Sep 2024 08:03:00 GMT Organization: Institut fuer Computersprachen, Technische Universitaet Wien Lines: 27 Message-ID: <2024Sep9.100300@mips.complang.tuwien.ac.at> References: <vbd6b9$g147$1@dont-email.me> <memo.20240905225550.19028d@jgd.cix.co.uk> <2024Sep6.080535@mips.complang.tuwien.ac.at> <vbiftm$ui9$1@gal.iecc.com> <2024Sep8.155511@mips.complang.tuwien.ac.at> <73c6d21457c487c61051ec52fe25ea5d@www.novabbs.org> <vbl3qj$22a2q$1@dont-email.me> Injection-Date: Mon, 09 Sep 2024 10:13:25 +0200 (CEST) Injection-Info: dont-email.me; posting-host="bff24d76364ca7ea0d223f91191d43fd"; logging-data="2463772"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+FCtdYySmYY046NXPNCVcE" Cancel-Lock: sha1:fcp+fD5iXGby8dDx3xApUy2C8r0= X-newsreader: xrn 10.11 Bytes: 2369 Lawrence D'Oliveiro <ldo@nz.invalid> writes: >Perhaps there is also the issue of the wildly-variable instruction length. >A single VAX operand descriptor could be up to 6 bytes; I think the >instruction with the most general-format operands could have 6 of them: >so, plus opcode, such an instruction could be 37 bytes long. The regularity of the VAX operand formats may actually help build the decoder: Decode your byte stream as possible operands, and then let the instruction decoder pick the real operands from the potential operands. >Even those who are talking about “post-RISC” are, I think, still in favour >of RISC-style fixed instruction lengths. Even among the RISCs, fixed instruction lengths are not universal: ARM T32 has two widths, as has RV64GC (and RISC-V has provisions for additional lengths, but AFAIK nobody uses them yet); there was also ROMP and MIPS16. Interestingly, despite their ample experience with T32, ARM went fixed-length with A64, but then the market for A64 is probably not as code-size sensitive as that for T32. - anton -- 'Anyone trying for "industrial quality" ISA should avoid undefined behavior.' Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>