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From: Michael S <already5chosen@yahoo.com>
Newsgroups: comp.arch
Subject: Re: Cost of handling misaligned access
Date: Mon, 24 Feb 2025 19:28:13 +0200
Organization: A noiseless patient Spider
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	logging-data="1176602"; mail-complaints-to="abuse@eternal-september.org";	posting-account="U2FsdGVkX1+7vhXfPKpRA8R+dUIfXpau6iaFxVwvLg8="
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On Mon, 24 Feb 2025 11:52:38 -0500
EricP <ThatWouldBeTelling@thevillage.com> wrote:

> Michael S wrote:
> > On Sun, 23 Feb 2025 11:13:53 -0500
> > EricP <ThatWouldBeTelling@thevillage.com> wrote:  
> >> It looks to me that Vivado intends that after you get your basic
> >> design working, this module optimization is *exactly* what one is
> >> supposed to do.
> >>
> >> In this case the prototype design establishes that you need
> >> multiple 64-bit adders and the generic ones synthesis spits out
> >> are slow. So you isolate that module off, use Verilog to drive the
> >> basic LE selections, then iterate doing relative LE placement
> >> specifiers, route the module, and when you get the fastest 64-bit
> >> adder you can then lock down the netlist and save the module
> >> design.
> >>
> >> Now you have a plug-in 64-bit adder module that runs at (I don't
> >> know the speed difference between Virtex and your Spartan-7 so
> >> wild guess) oh, say, 4 ns, to use multiple places... fetch,
> >> decode, alu, agu.
> >>
> >> Then plug that into your ALU, add in SUB, AND, OR, XOR, functions,
> >> isolate that module, optimize placement, route, lock down netlist,
> >> and now you have a 5 ns plug-in ALU module.
> >>
> >> Doing this you build up your own IP library of optimized hardware
> >> modules.
> >>
> >> As more and more modules are optimized the system synthesis gets
> >> faster because much of the fine grain work and routing is already
> >> done.
> >>  
> > 
> > 
> > It sounds like your 1st hand FPGA design experience is VERY
> > outdated.  
> 
> Never have, likely never will.
> Nothing against them - looks easier than wire-wrapping TTL and 4000
> CMOS. Though people do seem to spend an awful lot of time working
> around certain deficiencies like the lack of >1 write ports on
> register files, and the lack of CAM's. One would think market forces
> would induce at least one supplier to add these and take the fpga
> market by storm.
> 

Your view is probably skewed by talking to soft core hobbyists.
Please realize that most professionals do not care about
high-performance soft core. Soft core is for control plane functions
rather than for data plane. Important features are ease of use,
reliability, esp. of software tools and small size. Performance is
rated low. Performance per clock is rated even lower. So, professional
do not develop soft cores by themselves. And OTS cores that they use
are not superscalar. Quite often not even fully pipelined.
It means, no, small SRAM banks with two independent write ports is not
a feature that FPGA pros would be excited about.

> Also fpga's do seem prone to monopolistic locked-in pricing
> (though not really different from any relational database vendor).

Cheap Chinese clones of X&A FPGAs from late 2000s and very early 2010s
certainly exist. I didn't encounter Chinese clones of slightly newer
devices, like Xilinx 7-series. But I didn't look hard for them. So,
wouldn't be surprised if they exist, too.
Right now, and almost full decade back, neither X nor A cares about low
end. They just continue to ship old chips, mostly charging old price or
rising a little.

> At least with TTL one could do an RFQ to 5 or 10 different suppliers.
> 
> I'm just trying to figure out what these other folks are doing to get
> bleeding edge performance from essentially the same tools and similar
> chips.
> 
> I assume you are referring to the gui IDE interface for things like
> floor planning where you click on a LE cells and set some attributes.
> I also think I saw reference to locking down parts of the net list.
> But there are a lot of documents to go through.
> 

No, I mean florplanning, as well as most other manual physical-level
optimization are not used at all in 99% percents of FPGA designs that
started after year 2005.