Path: news.eternal-september.org!eternal-september.org!.POSTED!not-for-mail
From: anton@mips.complang.tuwien.ac.at (Anton Ertl)
Newsgroups: comp.arch
Subject: Re: Why I've Dropped In
Date: Wed, 11 Jun 2025 17:33:35 GMT
Organization: Institut fuer Computersprachen, Technische Universitaet Wien
Lines: 17
Message-ID: <2025Jun11.193335@mips.complang.tuwien.ac.at>
References: <0c857b8347f07f3a0ca61c403d0a8711@www.novabbs.com> <dd6e28b90190e249289add75780b204a@www.novabbs.com> <ec821d1d64555055271e3b72f241d39b@www.novabbs.com> <8addb3f96901904511fc9350c43917ef@www.novabbs.com> <102b5qh$1q55a$2@dont-email.me> <48c03284118d9d68d6ecf3c11b64a76b@www.novabbs.com>
Injection-Date: Wed, 11 Jun 2025 19:38:59 +0200 (CEST)
Injection-Info: dont-email.me; posting-host="57f666d6e50425e2714466424f197e29";
	logging-data="2226173"; mail-complaints-to="abuse@eternal-september.org";	posting-account="U2FsdGVkX1/bqY4/alhT3g0xfmY5vuvM"
Cancel-Lock: sha1:22tlrmB2QDx/9F9o706eD8bAJiQ=
X-newsreader: xrn 10.11

quadibloc <quadibloc@gmail.com> writes:
>However, if the memory reference instructions had 5 bits for the
>destination register, 5 bits for the index register, 5 bits for the base
>register, and 16 bits for the displacement, then there would only be one
>bit left for the opcode.

The solution of RISC architectures has been to not have displacement
and index registers at the same time (MIPS and its descendants do not
have base+index addressing at all).  The solution of CISC
architectures has been to allow bigger instructions, and possibly
different displacement sizes (e.g., 8 bits and 32 bits for IA-32 and
AMD64).

- anton
-- 
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>