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Path: ...!weretis.net!feeder9.news.weretis.net!news.nk.ca!rocksolid2!i2pn2.org!.POSTED!not-for-mail From: mitchalsup@aol.com (MitchAlsup1) Newsgroups: comp.arch Subject: Re: MSI interrupts Date: Mon, 24 Mar 2025 17:47:48 +0000 Organization: Rocksolid Light Message-ID: <24e503dc227d8b2bb0b68fd9ca8774b4@www.novabbs.org> References: <vqto79$335c6$1@dont-email.me> <fe9715fa347144df1e584463375107cf@www.novabbs.org> <vrhtkn$k7t$1@reader1.panix.com> <4603ec2d5082f16ab0588b4b9d6f96c7@www.novabbs.org> <vrrjlp$t52$1@reader1.panix.com> <pzdEP.126362$f5K3.26821@fx36.iad> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Info: i2pn2.org; logging-data="1577754"; mail-complaints-to="usenet@i2pn2.org"; posting-account="o5SwNDfMfYu6Mv4wwLiW6e/jbA93UAdzFodw5PEa6eU"; User-Agent: Rocksolid Light X-Rslight-Site: $2y$10$7A5avcZC7I1HAOwmy5QPKu6hQ1STeoQ.S2lCD.ca7my7r/.ZB69x2 X-Rslight-Posting-User: cb29269328a20fe5719ed6a1c397e21f651bda71 X-Spam-Checker-Version: SpamAssassin 4.0.0 Bytes: 3202 Lines: 46 On Mon, 24 Mar 2025 13:59:49 +0000, Scott Lurndal wrote: > cross@spitfire.i.gajendra.net (Dan Cross) writes: >>In article <4603ec2d5082f16ab0588b4b9d6f96c7@www.novabbs.org>, >>MitchAlsup1 <mitchalsup@aol.com> wrote: > >> >>>My architecture has a mechanism to perform ATOMIC stuff over multiple >>>instruction time frames that has the property that a higher priority >>>thread which interferers with a lower priority thread, the HPT wins >>>and the LPT fails its ATOMIC event. It is for exactly this reason >>>that I drag priority through the memory hierarchy--so that real-time >>>things remain closer to real-time (no or limited priority inversions). >> >>Without being able to see this in practice, it's difficult to >>speculate as to how well it will actually work in real-world >>scenarios. What is the scope of what's covered by this atomic >>thing? > > Sounds a lot like transactional memory. Something that has > yet to prove to be usable in the general case. It is not TM, but can be used to implement TM should you like. It is a set of instructions that can implement any (known) ATOMIC process (TestAndSet, TestAndTestAndSet; lock, unlock, LD-locked, ST-conditional, CompareSwap, CompareDouble, SwapDouble CompareTriple, SwapTriple, RemoveElement, InsertElement, MoveElement, ...} It is basically a recipe book so SW can implement whatever kinds of ATOMIC things SW wants, leaving HW out of the loop. you can also consider it a fully pipelined version of LDL and STC with up to 8 cache lines of data available for the event. >> >>Consider something as simple as popping an item off of the front >>of a queue and inserting it into an ordered singly-linked list: >>In this case, I'm probably going to want to take a lock on the >>queue, then lock the list, then pop the first element off of the >>queue by taking a pointer to the head. > > Which can be done with compare and exchange, atomically; > a lock may not be necessary. > > The insert into an ordered list will likely require a > spin lock (or a reader-writer lock of some form).