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From: john larkin <jl@650pot.com>
Newsgroups: sci.electronics.design
Subject: Re: An actual circuit
Date: Fri, 24 May 2024 11:46:04 -0700
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On Fri, 24 May 2024 20:33:55 +0200, Jeroen Belleman
<jeroen@nospam.please> wrote:

>On 5/24/24 17:59, Edward Rawde wrote:
>> "john larkin" <jl@650pot.com> wrote in message
>> news:bk815jh3skuecf1tap8o41rpgdh5kkq8o5@4ax.com...
>>> On Thu, 23 May 2024 13:06:46 -0700, john larkin <jl@650pot.com> wrote:
>>>
>>>> On Thu, 23 May 2024 15:35:00 -0400, "Edward Rawde"
>>>> <invalid@invalid.invalid> wrote:
>>>>
>>>>> I was having a conversation with a younger person who seemed to be of the
>>>>> view that to make an LED flash you would need something to decide when it
>>>>> should be on or off. So that would be some kind of software or digital
>>>>> system.
>> ...
>>>>
>>>
>>> The classic NPN astable circuit can hang up, with both transistors
>>> saturated. I wonder if he jfet circuit can hang too, with Idss
>>> grounding both drains and not enough gain to oscillate out of that
>>> state.
>>>
>>> Even when they have a hang state, luck usually kicks them off into
>>> oscillation. Your source resistors and  asymmetric drain resistors
>>> help it start up. Try making both drain resistors 3.3K.
>>>
>>> If you make the source resistors lower, it will hang up.
>>>
>> 
>> Yes I noticed both points when I was designing it.
>> I wanted to have it start up by itself, preferably without a kickstart
>> capacitor.
>> So I had a complicated circuit with two more diodes and a transistor in the
>> hope that I could detect the hang state and force it off balance.
>> I couldn't get that to work
>> Then I accidentally made R2 3,3k and R6 3.3k and I didn't see how it could
>> start so quickly with no other help.
>> Eventually I noticed 3,3k which maybe LTSpice takes as 3k.
>> 
>> If R2 and R6 are both 3.3k then LTSpice says it slowly drifts into operation
>> after 40 seconds.
>> But why does it go one way and not the other?
>> Is that an artefact of asymmetry in the simulation?
>> Or is there some hidden asymmetry in the circuit I'm not seeing when R2 is
>> 3.3k?
>
>Below are a pair of astable circuits. The left one is like yours,
>with a hangup state. I start it by specifying an initial condition.
>The right one will start all by itself.
>
>Jeroen Belleman

Instead of nailing the top end of the gate resistors to V+, one can
connect each to its own drain. That makes the fets go linear if they
are not oscillating.

Your right circuit sort of does that.