Path: ...!weretis.net!feeder9.news.weretis.net!i2pn.org!i2pn2.org!.POSTED!not-for-mail
From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: Interrupts in OoO
Date: Mon, 7 Oct 2024 21:21:24 +0000
Organization: Rocksolid Light
Message-ID: <30511637773541cec6c2119a23a71202@www.novabbs.org>
References: <2024Oct3.160055@mips.complang.tuwien.ac.at> <vdmrk6$3rksr$1@dont-email.me> <LyELO.69485$2nv5.62232@fx39.iad> <TdWLO.282116$FzW1.158190@fx14.iad> <963a276fd8d43e4212477cefae7f6e46@www.novabbs.org> <8IcMO.249144$v8v2.147178@fx18.iad> <2024Oct5.195712@mips.complang.tuwien.ac.at> <ve153q$1ptp0$1@dont-email.me> <35XMO.127329$WtV9.46848@fx10.iad>
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8; format=flowed
Content-Transfer-Encoding: 8bit
Injection-Info: i2pn2.org;
	logging-data="1020403"; mail-complaints-to="usenet@i2pn2.org";
	posting-account="o5SwNDfMfYu6Mv4wwLiW6e/jbA93UAdzFodw5PEa6eU";
User-Agent: Rocksolid Light
X-Spam-Checker-Version: SpamAssassin 4.0.0
X-Rslight-Posting-User: cb29269328a20fe5719ed6a1c397e21f651bda71
X-Rslight-Site: $2y$10$GaE5A9CazgaY.cclHggSa.vJqCo.8O.K43jbfIlBKHNIO2.CCKn3.
Bytes: 2521
Lines: 32

On Mon, 7 Oct 2024 19:59:59 +0000, Scott Lurndal wrote:

> Brett <ggtgp@yahoo.com> writes:
>>Anton Ertl <anton@mips.complang.tuwien.ac.at> wrote:

>>The CPU can give ring 0 priority, it is OoOe after all.
>
> I assume you're referring to the Intel 64-bit x86_64 family,
> as other processor families don't have a 'ring 0' per se.
>
> The AArch64 architecture provides the ability to configure
> the two processor interrupt signals to be delivered
> independently at any one of three privilege (exception)
> levels - kernel, hypervisor or secure monitor.

My 66000 provides the ability to configure any number of
interrupts (2^32) through any number of interrupt tables
(2^54) to any number of cores (2^16) at any of the 4
privilege levels and any of the 64 priority levels;

AND it requires no SW PIC updates on world-switches,
and control arrives in an already re-entrant state.

> Usually configured to route FIQ (Fast interrupt) to
> the most secure privilege level, and IRQ (interrupt)
> to the next most privileged level (hypervisor or
> bare metal OS).

Any interrupt in any table can be programmed to stimulate
any of the 4 (not just 3) privilege levels. User code
can be configured to take its own page faults without
an excursion through OS (except when called on by user
SVC).