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From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: Byte Addressability And Beyond
Date: Mon, 3 Jun 2024 22:34:46 +0000
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Michael S wrote:

> On Mon, 3 Jun 2024 18:01:00 -0000 (UTC)
> Thomas Koenig <tkoenig@netcologne.de> wrote:

>> Scott Lurndal <scott@slp53.sl.home> schrieb:
>> 
>> > Adding encryption (which of the dozen standard symmetric and
>> > asymmetric cipher algoritnms?)  
>> 
>> At the moment, AES.
>> 
>> > to a hardware device does increase complexity, and
>> > thus cost at the expense of extensibility (new algorithms come along
>> > periodically).  The cost of verifying crypto is a bit higher as it
>> > is very important to get correct when baking into gates.  
>> 
>> Seems to be fairly common these days, looking at
>> https://en.wikipedia.org/wiki/AES_instruction_set .
>> 
>> It appears that one round of AES fits fairly well into one cycle.

> One/cycle throughput fits well. Even two/cycle throughput fits. 
> One cycle latency does not fit unless you target very low frequency.
> Latency on POWER9 - 6 clocks. On majority of modern Intel and AMD cores
> 3-4 clocks. On Apple M1 - 3 clocks.


I agree here; You should consider encryption as smaller than an FMUL
unit
with about the characteristics of an FMUL. 1-cycle throughput 3-5 cycle

latency.