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From: john larkin <JL@gct.com>
Newsgroups: sci.electronics.design
Subject: Re: faster DDS clock
Date: Wed, 18 Sep 2024 20:57:39 -0700
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On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

>john larkin <JL@gct.com> wrote:
>> On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
>> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>> 
>>> john larkin <jl@650pot.com> wrote:
>>>> Assume a DAC being driven with an n-bit sine waveform at some clock
>>>> frequency, and then a lowpass filter and a comparator, generating a
>>>> programmable frequency clock.
>>>> 
>>>> Why not use both edges of the comparator output as our clock? That
>>>> de-stresses everything by 2:1, which could well be a net win on jitter
>>>> and such. Or gives twice the clock frequency with the same parts.
>>>> 
>>>> 
>>> 
>>> The usual trouble is that you have to get the other edge from somewhere. An
>>> xor gate and an RC is typical. 
>>> 
>>> Any asymmetry in the square wave turns into subharmonic jitter. 
>>> 
>>> A 2:1 PLL would probably get my vote. 
>
>> 
>> I'm trying to make things cheaper and simpler. I need a clock that's
>> programmable up to maybe 20 or 25 MHz, and it would be nice to use
>> some relatively cheap dual DACs.
>
>Understood.  A Joergesque solution would be to use a discrete FET as part
>of the RC + XOR, and dork the ON resistance to square up the duty cycle. 
>(He’d probably use a CD4007 DIY gate package to do a few at once. Maybe
>it’s possible to use a TinyLogic inverter with VDD open.)
>
>Cheers 
>
>Phil Hobbs 

An LVDS line receiver would make a pretty good comparator, after the
filter.

If I have enough balls (no pun intended) I can use an LVDS input of my
FPGA. One could even servo that to exactly 50%.

I don't know if this FPGA could internally clock on both edges.

But I can get a TI DAC908 for under $5, so may just clock that fast,
brute force at 100 MHz or so. That would make 20 MHz with a dinky
filter.