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From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: Computer architects leaving Intel...
Date: Wed, 4 Sep 2024 01:49:12 +0000
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On Sun, 1 Sep 2024 21:02:16 +0000, Paul A. Clayton wrote:

> On 8/31/24 4:56 PM, BGB wrote:
> [snip]
>> I was mostly doing dual-issue with a 4R2W design.
>>
>> Initially, 6R3W won out mostly because 4R2W disallows an indexed
>> store to be run in parallel with another op; but 6R3W did allow
>> this.
>
> Stores and MADD allow one register read to be delayed by at least
> one cycle. If the following cycle had a free read port, that could
> be stolen to complete the store/MADD. This could be viewed as
> cracking a three-source operation into a two-source operation and
> a one-source operation that reads source operands in a following
> cycle except that this operation never uses a result from the
> previous cycle.

Stores are allowed to delay the St.Data read until after retirement.
Thus, you are guaranteed that the cache line is present, that the
cache is in a hit state, and that the TLB has translated the address,
And finally, you need no forwarding on that read.