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From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: Byte Addressability And Beyond
Date: Wed, 1 May 2024 20:30:16 +0000
Organization: Rocksolid Light
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Michael S wrote:

> On Wed, 1 May 2024 16:38:09 +0000
> mitchalsup@aol.com (MitchAlsup1) wrote:

>> Lawrence D'Oliveiro wrote:
>> 
>> > On Wed, 1 May 2024 03:02:07 +0000, MitchAlsup1 wrote:  
>> 
>> >> I don't see what is wrong with loading a container with the field
>> >> and then extracting or inserting into the container.  
>> 
>> > You still need a place to put a bit offset for the base address of
>> > the field. Why not put it together with the rest of the address?  
>> 
>> Given a 20-40 year life of an architecture and the desire not to be
>> limited by addressability; I wanted and demanded of myself a full
>> 63-bit virtual address space per thread. Therefore, no bits in the
>> pointer are available for bit level addressing.
>> 

> At current rate of DRAM Moore's Law it does not look like anybody would
> need 63 bits 40 years from now. Arm's 55 or 56 bits will likely suffice
> for that long or longer.

The largest single system memory I can find quickly is 160TB or about 
47-bits of address space (I rounded down).

Given one can use CXL to coherently link multiples of such a system,
and not be limited by the number of pins dedicated to DRAM access;
40 years of growth at ½ a bit per year, already exceeds the 63-bit
address space (47+40/2 = 67 bits).

> The prospects of other byte-addresable types of memory looks even
> bleaker than DRAM's.

Agreed (baring some kind of miracle

> The only memory tech that is doing better is NAND flash, but it is
> inherently block-addressable.

And becomes the backing store.