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From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: Address bits again, Article on new mainframe use
Date: Wed, 4 Sep 2024 16:51:15 +0000
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On Wed, 4 Sep 2024 15:38:00 +0000, John Dallman wrote:

> In article <vb9r4g$2o1f$1@gal.iecc.com>, johnl@taugh.com (John Levine)
> wrote:
>
>> I think they thought it was paging, but of course 8K pages were way
>> too large.  So they overreacted and the Vax pages were 512 bytes
>> which were too small.
>
> Everyone seems to use 4K pages now, and that works well for
> ordinary-size
> programs in 32- and 64-bit address spaces. Bigger pages have been
> available in many operating systems for a couple of decades, but they
> seem to have been only used by programs that used memory in specialised
> ways, like database indexes, and they were used on a per-process basis.

For better or worse, My 66000 uses 8K pages.
This has several advantages::
a) it is a 5 level structure for a 63-bit virtual address space
   (instead of 6)
b) each level gives you 1024 DoubleWords (instead of 512)
   10 is easier for humans to reason about than 9
c) page sizes ae 8K, 8M, 8G, 8T, 8E, really big
   easier to reason through
d) nested page walks are 5×5 instead of 6×6
e) 1 more bit for doing something different.

With level skipping one can map 'cat" in 1 page of MMY tables
{one page of paging overhead}, and still scatter .code far from .data
and .stack or .heap.

> The interesting thing that's happening now is that Android 15, due for
> release soon, allows for devices that /only/ use 16K pages. Since
> there's
> no conventional paging, they presumably want to keep the page tables
> from
> eating too much RAM.
>
>> When I was working on the DOS version of Javelin we used a linker
>> that had overlays just like the mainframe linkers. I got it to work
>> and squeezed the code into about 1/3 the space it'd take otherwise
>> but it wasn't pleasant.
>
> Was that PLink, the Phoenix linker? The project I worked on in 1986-87
> used that for similar squashing.
>
> John