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From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: number of registers
Date: Tue, 20 Aug 2024 20:59:28 +0000
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On Tue, 20 Aug 2024 17:40:50 +0000, Michael S wrote:

> On Tue, 20 Aug 2024 16:40:06 +0000
> mitchalsup@aol.com (MitchAlsup1) wrote:
>
>>
>> and you may have
>> several of these in a local sequence of code.  ...
>
> No, you can not have several. It's always one then another one then yet
> another one etc... Each one can reuse the same temporary register.

The point is that the cost of not getting allocated into a register
is vastly lower--the count of instructions remains 1 while the
latency increases. That increase in latency does not hurt those
use once/seldom variables.

The the examples cited, the lack of register allocation triples
the instruction count due to lack of LD-OP and LD-OP-ST. The
register count I stated is how many registers would a
non-LD-OP machine need to break even on the instruction count.