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From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: Why I've Dropped In
Date: Wed, 11 Jun 2025 16:49:06 +0000
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On Wed, 11 Jun 2025 14:12:04 +0000, quadibloc wrote:

> On Wed, 11 Jun 2025 5:56:33 +0000, Thomas Koenig wrote:
>
>> Having different classes of base and index registers is very
>> un-RISCy, and not generally a good idea.  General purpose registers
>> is one of the great things that the /360 got right, as the VAX
>> later did, and the 68000 didn't.
>
> This is true.
>
> However, if the memory reference instructions had 5 bits for the
> destination register, 5 bits for the index register, 5 bits for the base
> register, and 16 bits for the displacement, then there would only be one
> bit left for the opcode.

And that is why you don't do it that way.

We can all agree that [Rbase+Rindex<<scale+Displacement] is (IS) the
proper way to abstract address-generation. The problem is how does
one "get there". Another way to look at this is that the AGEN unit
is built to do index scaling AND to do DISPlacement addition as its
primitive. The rest is routing of operands to AGEN--and in this case
we KNOW that DISP is a constant at DECODE time and can address its
instruction-queueing appropriately.

In my case I broke it into 2 sets of patterns::

     MEM   Rd,[Rbase+DISP16]
and
     MEM   Rd,[Rbase+Rindex<<scale]

both of which fit in 32-bits. With 6-bit Major OpCode, this eats
up 3/8ths of the OpCode space (There are 2× as many LDs as STs)
in the Major OpCode repository. THEN one finds a way to add
DISP32 and DISP64 (or ABS64) constants to the second form.

DISP16 covers 70%-ile of memory references, base+index covers
another 20%-ile, so one only needs [b+i<<s+DISP] 5%-10% of the
time. But every time you can use it it save executing another
instruction (sometimes 2).

> As I required 5 bits for the opcode to allow both loads and stores for
> several sizes each of integer and floating-point operands, I had to save
> bits somewhere.

My LDs are content free (LDs don't care if they are loading
integer, or floating point data, or SIMD data, ...

> Therefore, I reduced the index register and base register fields to
> three bits each, using only some of the 32 integer registers for those
> purposes.

This is going to hurt register allocation.

> A standard RISC would not have an index register field, only a base
> register field, meaning array accesses would require multiple
> instructions.
>
> The 68000 only had base-index addressing with an 8-bit displacement;
> true base-index addressing with a normal displacement arrived in the
> 68020, but the instructions using it took up 48 bits.
>
> I'll agree the 68000 architecture did have a serious mistake. It was
> CISC, so it didn't need to be RISC-like, but the special address
> registers should only have been used as base registers; the regular
> arithmetic registers should have been the ones used as index registers,
> since one has to do arithmetic to produce valid index values.
>
> The separate address registers would then have been useful, by allowing
> those of the eight (rather than 16 or 32) general registers that would
> have been used up holding static base register values to be freed up.
>
> John Savard