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Path: ...!news.mixmin.net!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: John Savard <quadibloc@servername.invalid> Newsgroups: comp.arch Subject: Re: Oops (Concertina II Going Around in Circles) Date: Wed, 08 May 2024 02:01:07 -0600 Organization: A noiseless patient Spider Lines: 44 Message-ID: <5kbm3j51lc821oo9lhj4inljh30odoijo4@4ax.com> References: <kipj2j5be9kuv8rn770iq6neq2cvu3s5oi@4ax.com> <b936220e0d198db43b18e58007401f42@www.novabbs.org> <6qam3jplo8oa9n46g70c48tn69ao8hn486@4ax.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Date: Wed, 08 May 2024 10:01:09 +0200 (CEST) Injection-Info: dont-email.me; posting-host="f337ba56f9b9ca0be2fd83be8efec5e4"; logging-data="4047987"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/iVj0iYEhxlIWyW4oolzOfMMvVdYkuxfA=" Cancel-Lock: sha1:A7jnQp8N0IFF8cuB6Efwa0/nhEk= X-Newsreader: Forte Free Agent 3.3/32.846 Bytes: 3081 On Wed, 08 May 2024 01:46:41 -0600, John Savard <quadibloc@servername.invalid> wrote: >Why are my various iterations of Concertina II _all_, consistently, >"full to the brim"? >I can always add one new type of header which specifies alternate >instructions with fairly low overhead... and then, at a modest cost, >even the most enormous new feature can have its own 32-bit >instructions! That only answersl a part of that question - why I feel I can _get away_ with having an ISA that is "full to the brim". But why did I let it get that way in the first place? Well, the reason for that is actually quite simple. Because a major design goal of Concertina II is to offer as much as possible of the basic operations required of a computer in instructions of the shortest possible length. 16-bit displacements are the norm in microprocessor instruction sets, so I offer them. I offer base-index addressing - which microprocessors usually don't - because I feel it's needed for using arrays. And I have register banks of 32 registers because that's what today's RISC machines do. All of that means that the load and store instructions - particularly when integer load and store also include load unsigned and insert - take up 3/4 of all 32-bit instructions (approximately; one doesn't need unsigned load and insert for the 64-bit integer type, because it fills the register). And that's with using only 8 of the 32 registers for the base register and the index register each. Some parts of the instruction set do have slack. Two-address register-to-register operate instructions have a large opcode field, so there is some room for future expansion in parts of the instruction set. But, basically, it takes all the available bits to offer the level of functionality I am trying to provide with the basic 32-bit instruction set. Since that covers the traditional functionality of a CPU - floating-point and integer types - nothing basic is missing. John Savard