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Date: Tue, 11 Feb 2025 11:55:53 -0500
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Subject: Re: SPLD output current protection
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From: bitrex <user@example.net>
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On 2/11/2025 10:50 AM, john larkin wrote:
> On Mon, 10 Feb 2025 22:59:23 -0500, bitrex <user@example.net> wrote:
> 
>> On 2/10/2025 10:41 PM, john larkin wrote:
>>> On Mon, 10 Feb 2025 17:57:06 -0500, bitrex <user@example.net> wrote:
>>>
>>>> I have an SPLD with about 8 terminals exposed to the user I'd like to
>>>> protect against over current. They're very low-speed outputs (10s of Hz
>>>> at most), don't really want to spend a bunch for a chip like the L6374
>>>> as an intermediary, or the board space for a bunch of transistors to
>>>> discrete limit...
>>>>
>>>> The SPLD has a max per-chip-side Vdd input current of 45 mA at 85 C TJ
>>>> and 22 mA at 110 TJ, and can sink 86 mA to ground per side, 41 at 110 TJ.
>>>>
>>>> The outputs are configured as push-pull or open drain, depending on the
>>>> firmware/application, either way they can source or sink 40mA in
>>>> isolation. But no more than two outputs per side at a time will be in a
>>>> state such that they can sink/source current either way.
>>>>
>>>> The uP I'm using has a very nice 10 bit differential ADC (9 bits if used
>>>> in bipolar mode) I'm thinking about just rigging it to two 4051s to
>>>> "scan" a current sense in each output line to implement the overcurrent,
>>>> can set different thresholds based on whether it's configured push-pull
>>>> or OD, but what might conservative limits be? And what rate to scan?
>>>>
>>>> The SPLD is acting as a simple power supervisor and has a PWR GOOD line
>>>> to bring up the uP. In turn it gets a clock from the uP, I can set up
>>>> the SPLD to set all those outputs hi-z if it ever loses the clock (i.e.
>>>> uP hangs) as an extra layer of protection..
>>>
>>> What's an SPLD?
>>>
>>>
>>
>> If it ain't a FPGA or a CPLD it's an SPLD. I think.
> 
> What part is it? It seems to have power drive beyond what an FPGA
> would have.
> 

I use these a lot:

<https://www.renesas.com/en/products/programmable-mixed-signal-asic-ip-products/greenpak-programmable-mixed-signal-products/greenpak-asynchronous-state-machine/slg46537-greenpak-programmable-mixed-signal-matrix-asynchronous-state-machine>

They're cheap enough in quantity to use as general output expanders and 
the pins have more configurable options than the average uP tends to; 
push-pull, NMOS open drain, PMOS open drain, 1x,2x,4x drive depending on 
the pin, with 10k, 100k, 1Meg or floating selectable for pull-up/pull down.

The async state machine is a nice add-on and one can do some e.g. power 
sequencing with that.