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From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: Constant Stack Canaries
Date: Fri, 4 Apr 2025 21:13:27 +0000
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On Fri, 4 Apr 2025 3:49:31 +0000, Robert Finch wrote:

> On 2025-04-03 1:22 p.m., BGB wrote:
-------------------
>>
>> Or, to allow for NOMMU operation, or reduce costs by not having context
>> switches result in as large of numbers of TLB misses.
>>
>> Also makes the kernel simpler as it doesn't need to deal with each
>> process having its own address space.
>
> Have you seen the MPRV bit in RISCV? Allows memory ops to execute using
> the previous mode / address space. The bit just has to be set, then do
> the memory op, then reset the bit. Makes it easy to access data using
> the process address space.

Let us postulate you are running in RISC-V HyperVisor on core[j]
and you want to write into GuestOS VAS and into application VAS
more or less simultaneously.

Seems to me like you need a MPRV to be more than a single bit
so it could index which layer of the SW stack's VAS it needs
to touch.