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Path: news.eternal-september.org!eternal-september.org!feeder3.eternal-september.org!i2pn.org!i2pn2.org!.POSTED!not-for-mail From: quadibloc <quadibloc@gmail.com> Newsgroups: comp.arch Subject: Re: Why I've Dropped In Date: Tue, 17 Jun 2025 01:07:25 +0000 Organization: novaBBS Message-ID: <6ac6d4611281f9f350b0595a87d367e6@www.novabbs.com> References: <0c857b8347f07f3a0ca61c403d0a8711@www.novabbs.com> <dd6e28b90190e249289add75780b204a@www.novabbs.com> <ec821d1d64555055271e3b72f241d39b@www.novabbs.com> <8addb3f96901904511fc9350c43917ef@www.novabbs.com> <102b5qh$1q55a$2@dont-email.me> <48c03284118d9d68d6ecf3c11b64a76b@www.novabbs.com> <577246053d33788ee71e2e04e8466450@www.novabbs.org> <jwvecvjacof.fsf-monnier+comp.arch@gnu.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Info: i2pn2.org; logging-data="820150"; mail-complaints-to="usenet@i2pn2.org"; posting-account="GSAUMsvIs05PgSAevbIzdWiOy1BcuThtiv166p5NnMk"; User-Agent: Rocksolid Light X-Spam-Checker-Version: SpamAssassin 4.0.0 X-Rslight-Posting-User: 7260c650ae4d5ba82d3b6b1eab0ac1b8653ff052 X-Rslight-Site: $2y$10$0A59Bx7dMM1t47C4US3ltOQpvKB7ZOdwIICMAsF/AS/lq62D/VS8e On Mon, 16 Jun 2025 16:17:21 +0000, Stefan Monnier wrote: > I vaguely remember reading somewhere that it doesn't have to be too bad: > e.g. if you reduce register-specifiers to just 4bits for a 32-register > architecture and kind of "randomize" which of the 16 values refer to > which of the 32 registers for each instruction, it's fairly easy to > adjust a register allocator to handle this correctly (assuming you > choose your instructions beforehand, you simply mark, for each > instructions, the unusable registers as "interfering"), and the end > result is often almost as good as if you had 5bits to specify > the registers. No doubt this is an intriguing theoretical possibility, but even I would shrink from inflicting something so bizarre upon programmers and compiler writers. John Savard