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From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: why bits, Byte Addressability And Beyond
Date: Tue, 7 May 2024 00:57:00 +0000
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John Levine wrote:

> According to John Savard  <quadibloc@servername.invalid>:
>>On Mon, 6 May 2024 02:54:11 -0000 (UTC), John Levine <johnl@taugh.com>
>>wrote:
>>
>>>Why do you think bit addressing will be
>>>faster than shifting and masking? ...

>>So just because a processor has a 64-bit bus to memory doesn't mean it
>>has to implement fetching a single byte from memory by doing a shift
>>and mask operation in a 64-bit register. Instead, each byte of the bus
>>could have a direct wired path to the low 8-bits of the internal data
>>bus feeding the registers.

> I was more thinking about storing bit fields, where you probably have
> to fetch the whole word or cache line or whatever, shift the new field
> into it, and then store it back. You already have to do something like
> that for byte stores but bit addressing makes it 8 times as hairy.

Which is no different than ECC, BTW...

Could someone invent a bit field ISA that was as efficient as a byte
accessible architecture:: probably.

Could this bit accessible architecture outperform a byte ISA on
typical codes:: doubtful. Two reasons:: 1) more delay in the 
LD/ST pipeline, 2) most programs use as little bit-fielding as
possible (not as much as practical) !!!