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Path: ...!weretis.net!feeder9.news.weretis.net!i2pn.org!i2pn2.org!.POSTED!not-for-mail From: mitchalsup@aol.com (MitchAlsup1) Newsgroups: comp.arch Subject: Re: Tonights Tradeoff Date: Fri, 13 Sep 2024 17:09:48 +0000 Organization: Rocksolid Light Message-ID: <7512f495fa0f7e11f8ad2b98168c064c@www.novabbs.org> References: <vbgdms$152jq$1@dont-email.me> <17537125c53e616e22f772e5bcd61943@www.novabbs.org> <vbj5af$1puhu$1@dont-email.me> <a37e9bd652d7674493750ccc04674759@www.novabbs.org> <vbog6d$2p2rc$1@dont-email.me> <vboqpp$2r5v4$1@dont-email.me> <vbpmqr$30vto$1@dont-email.me> <vbqcds$35l1q$2@dont-email.me> <vbs7ff$3koub$1@dont-email.me> <vbse3j$f01n$2@dont-email.me> <vbtnlj$22nu$1@dont-email.me> <718895dfd5c344865453f710367501ba@www.novabbs.org> <vbvfcm$d2he$1@dont-email.me> <9f0a142454e6ab2f1d1985e3af116b4b@www.novabbs.org> <aAYEO.4182$T4b4.1801@fx34.iad> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Info: i2pn2.org; logging-data="1930266"; mail-complaints-to="usenet@i2pn2.org"; posting-account="65wTazMNTleAJDh/pRqmKE7ADni/0wesT78+pyiDW8A"; User-Agent: Rocksolid Light X-Rslight-Site: $2y$10$PsFcj2TkAihW14UZ3IqTMey2g1OCXNUEvxw2ITz3yvfU60e9Js4ra X-Rslight-Posting-User: ac58ceb75ea22753186dae54d967fed894c3dce8 X-Spam-Checker-Version: SpamAssassin 4.0.0 Bytes: 2682 Lines: 27 On Fri, 13 Sep 2024 15:08:42 +0000, EricP wrote: > MitchAlsup1 wrote: >> On Thu, 12 Sep 2024 19:28:19 +0000, Robert Finch wrote: >> >>> Would not want to queue to the reorder buffer from the alternate path, >>> as there is a bit of a bottleneck at queue. Not wondering what to do >>> about multiple branches. Multiple pipelines and more switches? Front-end >>> would look like a pipeline tree to handle multiple outstanding branches. >>> >>> Was wondering what to do with the extra fetch bandwidth. Fetching two >>> cache-lines at once means there may have been up to 21 instructions >>> fetched. But its only a four-wide machine. >> >> For my 6-wide machine I am fetching 1/2 a cache line twice for the >> sequential path and 1/2 a cache line for the alternate path from >> an 8 banked ICache. > > Why 8 banks if you are fetching just three 32-byte buffers at once? > I suppose 8 minimizes the chance of colliding on a bank access. > Still, it seems like 4 banks would be sufficient. 3 banks for the predicted fetch stuff, 1-2 banks for the mispredicted fetches. You not only fetch instructions on the predicted directions, you fetch instructions on the predicted non-taken directions so they are ready for insertion should that branch need backup.