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From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: Tonights Tradeoff
Date: Fri, 13 Sep 2024 17:09:48 +0000
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On Fri, 13 Sep 2024 15:08:42 +0000, EricP wrote:

> MitchAlsup1 wrote:
>> On Thu, 12 Sep 2024 19:28:19 +0000, Robert Finch wrote:
>>
>>> Would not want to queue to the reorder buffer from the alternate path,
>>> as there is a bit of a bottleneck at queue. Not wondering what to do
>>> about multiple branches. Multiple pipelines and more switches? Front-end
>>> would look like a pipeline tree to handle multiple outstanding branches.
>>>
>>> Was wondering what to do with the extra fetch bandwidth. Fetching two
>>> cache-lines at once means there may have been up to 21 instructions
>>> fetched. But its only a four-wide machine.
>>
>> For my 6-wide machine I am fetching 1/2 a cache line twice for the
>> sequential path and 1/2 a cache line for the alternate path from
>> an 8 banked ICache.
>
> Why 8 banks if you are fetching just three 32-byte buffers at once?
> I suppose 8 minimizes the chance of colliding on a bank access.
> Still, it seems like 4 banks would be sufficient.

3 banks for the predicted fetch stuff, 1-2 banks for the mispredicted
fetches.

You not only fetch instructions on the predicted directions, you fetch
instructions on the predicted non-taken directions so they are ready
for insertion should that branch need backup.