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From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: Tonights Tradeoff - Background Execution Buffers
Date: Sat, 5 Oct 2024 23:02:28 +0000
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On Fri, 4 Oct 2024 4:04:20 +0000, Robert Finch wrote:

> Today I am wondering how many predicate registers are enough.

Realistically 3 as long as they are orthogonal to each other and to
code.

>                                                               Scanning
> webpages reveals a variety. The Itanium has 64-predicates, but they are
> used for modulo loops and rotated. Rotating register is Itaniums method
> of register renaming, so it needs more visible registers. In a classic
> superscalar design with a RAT where registers are renamed, it seems like
> 64 would be far too many. Cray had eight vector mask registers.

In the ECL logic CRAY used an 8:1 multiplexer costs no more than a
2:1 multiplexer in power and gate count.

>                                                                 I think
> the RISCV- Hwatcha has 16 if I looked at the diagram correctly.
> I cannot see the compiler making use of very many predicate registers
> simultaneously. Since they are not used simultaneously, and register
> renaming is in effect, there should not be a great need for predicate
> registers.

With the orthogonality mentioned above, 3 covers a tree with 8 branches
or a 3-deep if()then{}else[}.

> Suppose one wants predicated logic in a loop with the predicate being
> set outside of the loop.

1 decision per predicate,

>                          It may be desirable to have several blocks of
> logic predicated by different predicates in the loop. It is likely
> desirable to have more than one predicate then.
> ->Reserved four bits in the instruction for predicates. Do not want to
> waste bits though. Using a 64-bit instruction.