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From: John Savard <quadibloc@servername.invalid>
Newsgroups: comp.arch
Subject: Re: Oops (Concertina II Going Around in Circles)
Date: Fri, 10 May 2024 18:34:09 -0600
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On Fri, 10 May 2024 21:06:58 +0000, mitchalsup@aol.com (MitchAlsup1)
wrote:
>John Savard wrote:

>> Now that I think I can finally wrap up Concertina II, having found how
>> to achieve its goals as best as possible, I can go on to Concertina
>> III... and, given your anguished pleas, I _will_ give up on block
>> structure for the next iteration.

>Would you like to read My 66000 ISA while taking a break between CT II and
>CT III ??

Oh, yes, indeed, although I don't promise to shamelessly steal all
your good ideas.

I am going to try to somehow squeeze immediates in while keeping
instuction length decoding relatively simple. That, I fear, is not
going to be easy for me, although I outlined a scheme before which I
feel is not simple enough.

>> In order to do that, though, it will have to be CISC, not RISC...
>> banks of 8 registes, sort of like Concertina I, but much less messy.

>With MEM-OPs are you not already CISC ??

I should have been clearer, but to tell the truth would have taken
many words.

What I meant was that while Concertina II indeed is hardly RISC, it
still contains a near-RISC instruction set in the basic 32-bit
operations. Unlike typical RISC instruction sets, it has base plus
index addressing, though.

Then mem-ops are added in the first supplementary instruction set,
yes. Concertina II is intended to be "architecture-agnostic", being at
once sort of like RISC, but also VLIW and CISC.

What Concertina III would give up, to no longer be RISC at all, would
be register banks of 32 registers. Changing that to 8 registers
shortens certain fields, letting me switch to native variable-length
instructions without the need for any block header mechanism.

John Savard