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From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: Arm ldaxr / stxr loop question
Date: Thu, 31 Oct 2024 19:12:43 +0000
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On Mon, 28 Oct 2024 19:13:03 +0000, jseigh wrote:

> So if were to implement a spinlock using the above instructions
> something along the lines of
>
> ..L0
> 	ldaxr    -- load lockword exclusive w/ acquire membar
> 	cmp      -- compare to zero
> 	bne  .LO -- loop if currently locked
>          stxr     -- store 1
>          cbnz .LO -- retry if stxr failed
>
> The "lock" operation has memory order acquire semantics and
> we see that in part in the ldaxr but the store isn't part
> of that.  We could append an additional acquire memory barrier
> but would that be necessary.
>
> Loads from the locked critical region could move forward of
> the stxr but there's a control dependency from cbnz branch
> instruction so they would be speculative loads until the
> loop exited.
>
> You'd still potentially have loads before the store of
> the lockword but in this case that's not a problem
> since it's known the lockword was 0 and no stores
> from prior locked code could occur.
>
> This should be analogous to rmw atomics like CAS but
> I've no idea what the internal hardware implementations
> are.  Though on platforms without CAS the C11 atomics
> are implemented with LD/SC logic.
>
> Is this sort of what's going on or is the explicit
> acquire memory barrier still needed?
>
> Joe Seigh

My guess is that so few of us understand ARM fence
mechanics that we cannot address teh asked question.