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From: Keith Thompson <Keith.S.Thompson+u@gmail.com>
Newsgroups: comp.arch
Subject: Re: What do we call non-pipelined designs?
Date: Sun, 08 Dec 2024 18:45:09 -0800
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Marcus <m.delete@this.bitsnbites.eu> writes:
> I usually (and simplistically) divide CPU designs (implementations) into
> two main categories:
>
> - Pipelined
> - Non-pipelined
>
> Of course, there is a sliding scale at play, but let's not get into that
> debate.
>
> My question is: What is the best name for non-pipelined designs?

I can't think of anything better or clearer than "non-pipelined designs".

> I'm thinking about CPU:s that transition through several states (one
> clock cycle after another) when executing a single instruction (e.g.
> FETCH + DECODE + EXECUTE), and where instruction and data typically
> share the same memory interface.

-- 
Keith Thompson (The_Other_Keith) Keith.S.Thompson+u@gmail.com
void Void(void) { Void(); } /* The recursive call of the void */