Path: ...!news.misty.com!weretis.net!feeder9.news.weretis.net!i2pn.org!i2pn2.org!.POSTED!not-for-mail
From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: My 66000 and High word facility
Date: Wed, 14 Aug 2024 22:06:46 +0000
Organization: Rocksolid Light
Message-ID: <8a7fbffe53e5b09ebac78a17b690d744@www.novabbs.org>
References: <v98asi$rulo$1@dont-email.me> <38055f09c5d32ab77b9e3f1c7b979fb4@www.novabbs.org> <v991kh$vu8g$1@dont-email.me> <2024Aug11.163333@mips.complang.tuwien.ac.at>
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8; format=flowed
Content-Transfer-Encoding: 8bit
Injection-Info: i2pn2.org;
	logging-data="2595498"; mail-complaints-to="usenet@i2pn2.org";
	posting-account="65wTazMNTleAJDh/pRqmKE7ADni/0wesT78+pyiDW8A";
User-Agent: Rocksolid Light
X-Rslight-Posting-User: ac58ceb75ea22753186dae54d967fed894c3dce8
X-Rslight-Site: $2y$10$kLI6uHzvP64EfrpGQaTOQOY9pWHShIz4DdjL9fSbZ67t.hOjnpcEC
X-Spam-Checker-Version: SpamAssassin 4.0.0
Bytes: 2434
Lines: 39

On Sun, 11 Aug 2024 14:33:33 +0000, Anton Ertl wrote:

> Brett <ggtgp@yahoo.com> writes:
>>The lack of CPU’s with 64 registers is what makes for a market, that 4%
>>that could benefit have no options to pick from.
>
> They had:
>
> SPARC: Ok, only 32 GPRs available at a time, but more in hardware
> through the Window mechanism.

SPARCs FPGA through UltraSPARC used 1 full cycle to access the windowed
register file will MIPS, 88K, and early Alphas used 1/2 cycle. So SPARC
architecture saddled them with an inherent disadvantage....

> AMD29K: IIRC a 128-register stack and 64 additional registers

Similar issues.

> IA-64: 128 GPRs and 128 FPRs with register stack and rotating register
> files to make good use of them.

Don't know for certain, but I would expect the same as above.

> The additional registers obviously did not give these architectures a
> decisive advantage.

Captain Obvious strikes again

Oh, and BTW, that 1/2 cycle of delay getting started should have cost
~5% IPC. But SAPRC never achieved high clock frequencies nor dis IA-64.

> When ARM designed A64, when the RISC-V people designed RISC-V, and
> when Intel designed APX, each of them had the opportinity to go for 64
> GPRs, but they decided not to.  Apparently the benefits do not
> outweigh the disadvantages.
>
> Where is your 4% number coming from?
>
> - anton