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From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: Is Intel exceptionally unsuccessful as an architecture
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Date: Tue, 24 Sep 2024 03:03:16 +0000
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On Tue, 24 Sep 2024 2:48:43 +0000, Chris M. Thomasson wrote:

> On 9/23/2024 5:26 PM, MitchAlsup1 wrote:
>> On Mon, 23 Sep 2024 22:46:47 +0000, Chris M. Thomasson wrote:
>>
>>> On 9/23/2024 3:32 PM, MitchAlsup1 wrote:
>>
>>>>
>>>> I got rid of all MemBars and still have a fairly relaxed memory model.
>>>
>>> That is interesting to me! It's sort-of "out of the box" so to speak?
>>> How can a programmer take advantage of the relaxed aspect of your model?
>>>
>> Touch a DRAM location and one gets causal order.
>> Touch a MM I/O location and one gets sequential consistency
>> Touch a config space location and one gets strongly ordering
>> Touch ROM and one gets unordered access.
>>
>> You see, the memory <ordering> model is not tied to a CPU state, but
>> to what LD and ST instructions touch.
> [...]
>
> What is the granularity of the "touch"? A L2 cache line?

Yes.