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From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: Arm ldaxr / stxr loop question
Date: Wed, 13 Nov 2024 00:29:42 +0000
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On Tue, 12 Nov 2024 23:02:13 +0000, aph@littlepinkcloud.invalid wrote:

> Chris M. Thomasson <chris.m.thomasson.1@gmail.com> wrote:
>> On 11/12/2024 4:14 AM, aph@littlepinkcloud.invalid wrote:
>>>
>>> One other thing to be aware of is that the StoreLoad barrier needed
>>> for sequential consistency is logically part of an LDAR, not part of a
>>> STLR. This is an optimization, because the purpose of a StoreLoad in
>>> that situation is to prevent you from seeing your own stores to a
>>> location before everyone else sees them.
>>
>> Fwiw, even x86/x64 needs StoreLoad when an algorithm depends on a
>> store followed by a load to another location to hold. LoadStore is
>> not strong enough. The SMR algorithm needs that. Iirc, Peterson's
>> algorithms needs it as well.
>
> That's right, but my point about LDAR on AArch64 is that you can get
> sequential consistency without needing a StoreLoad. LDAR can peek
> inside the store buffer and, much of the time, determine that it isn't
> necessary to do a flush. I don't know if Arm were the first to do
> this, but I don't recall seeing it before. It is a brilliant idea.

1990-1992: I was working on Mc88120. It had a conditional cache--a
place to store store-data until the store instruction became consistent.
After becoming consistent, the store data would migrate to L1 or on
to DRAM, ... This structure could be probed for memory order rather
similar to what ARM is doing.
>
> Andrew.