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Path: ...!weretis.net!feeder9.news.weretis.net!i2pn.org!i2pn2.org!.POSTED!not-for-mail From: mitchalsup@aol.com (MitchAlsup1) Newsgroups: comp.arch Subject: Re: Is Intel exceptionally unsuccessful as an architecture =?UTF-8?B?ZGVzaWduZXI/?= Date: Fri, 20 Sep 2024 22:11:05 +0000 Organization: Rocksolid Light Message-ID: <920c561c4e39e91d3730b6aab103459b@www.novabbs.org> References: <memo.20240913205156.19028s@jgd.cix.co.uk> <vcd3ds$3o6ae$2@dont-email.me> <2935676af968e40e7cad204d40cafdcf@www.novabbs.org> <vcd7pr$3op6a$3@dont-email.me> <a20365f1bdcad769edd9e1f840edb2fe@www.novabbs.org> <vcda96$3p3a7$2@dont-email.me> <21028ed32d20f0eea9a754fafdb64e45@www.novabbs.org> <RECGO.45463$xO0f.22925@fx48.iad> <20240918190027.00003e4e@yahoo.com> <vcfp2q$8glq$5@dont-email.me> <jwv34lumjz7.fsf-monnier+comp.arch@gnu.org> <vckpkg$18k7r$2@dont-email.me> <vckqus$18j12$2@dont-email.me> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Info: i2pn2.org; logging-data="2815020"; mail-complaints-to="usenet@i2pn2.org"; posting-account="65wTazMNTleAJDh/pRqmKE7ADni/0wesT78+pyiDW8A"; User-Agent: Rocksolid Light X-Rslight-Site: $2y$10$iYuQ.4nlLRraTPTB2jzpTORUWP3hXSBCSLj4xC1xoXlTEbVPrfuU6 X-Rslight-Posting-User: ac58ceb75ea22753186dae54d967fed894c3dce8 X-Spam-Checker-Version: SpamAssassin 4.0.0 Bytes: 2482 Lines: 26 On Fri, 20 Sep 2024 21:54:36 +0000, Chris M. Thomasson wrote: > On 9/20/2024 2:32 PM, Lawrence D'Oliveiro wrote: >> On Fri, 20 Sep 2024 11:21:52 -0400, Stefan Monnier wrote: >> >>>> The basic issue is: >>>> * CPU+motherboard RAM -- usually upgradeable >>>> * Addon coprocessor RAM -- usually not upgradeable >>> >>> Maybe the RAM of the "addon coprocessor" is not upgradeable, but the >>> addon board itself can be replaced with another one (one with more RAM). >> >> Yes, but that’s a lot more expensive. > > I had this crazy idea of putting cpus right on the ram. So, if you add > more memory to your system you automatically get more cpu's... Think > NUMA for a moment... ;^) Can software use the extra CPUs ? Also note: DRAMs are made on P-Channel process (leakage) with only a few layer of metal while CPUs are based on a N-Channel process (speed) with many layers of metal. Bus interconnects are not setup to take a CPU cache miss from one DRAM to a different DRAM on behalf of its contained CPU(s). {Chicken and egg problem}