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Path: ...!weretis.net!feeder9.news.weretis.net!news.nk.ca!rocksolid2!i2pn2.org!.POSTED!not-for-mail From: mitchalsup@aol.com (MitchAlsup1) Newsgroups: comp.arch Subject: Re: PCIe MSI-X interrupts Date: Wed, 10 Jul 2024 17:59:46 +0000 Organization: Rocksolid Light Message-ID: <922220c8593353c7ed0fda9e656d359d@www.novabbs.org> References: <bb16865f7675526d4e2b87283e28c2c5@www.novabbs.org> <sKmdO.62321$G9_a.28048@fx13.iad> <bejeO.24905$Gurd.6236@fx34.iad> <8JkeO.30075$WaKd.3069@fx41.iad> <f9e2c222349934ce0d6d9cda5b55f8b7@www.novabbs.org> <FNzeO.141608$Cqra.114681@fx10.iad> <09dac1eb164a4c5226036cbde84884da@www.novabbs.org> <20240627112720.00005063@yahoo.com> <%LdfO.108407$xKj1.7795@fx09.iad> <ecd43e7ed4d3cc6fcc3bca3a999725e8@www.novabbs.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Info: i2pn2.org; logging-data="2824188"; mail-complaints-to="usenet@i2pn2.org"; posting-account="65wTazMNTleAJDh/pRqmKE7ADni/0wesT78+pyiDW8A"; User-Agent: Rocksolid Light X-Spam-Checker-Version: SpamAssassin 4.0.0 X-Rslight-Posting-User: ac58ceb75ea22753186dae54d967fed894c3dce8 X-Rslight-Site: $2y$10$Ix4esPDQFQktb7ChZ8N1SuUmXnNmWJjTWMZntW.EqRMEOhuVKddI6 Bytes: 2676 Lines: 37 On page 43 of:: https://www.cs.uml.edu/~bill/cs520/slides_15E_PCI_Express_IOV.pdf it states: "Must not indicate an invalidation has completed until all outstanding Read Requests that reference the associated translation have retired" "Must insure that the invalidation completion indication to RC will arrive at the RC after previously posted writes that use the stale address." and "...If transactions are in a queue waiting to be sent, It is not necessary for the device to expunge requests from the queue even if those transaction[s] use an address that is being invalidated." The first 2 seem to be PCIe ordering requirements between EP and RC. The 3rd seems to say if EP used a translation while it was valid, then its invalidation does not prevent requests using the now stale translation. So, a SATA device could receive a command to read a page into memory. SATA EP requests ATS for the translation of the given virtual address to the physical page. Then the EP creates a queue of write requests filling in the addr while waiting on data. Once said queue has been filled, and before the data comes off the disk, an invalidation arrives and is ACKed. The data is still allowed to write into memory. {{But any new command to the SATA device would not be allowed to use the translation.}} Is this a reasonable interpretation of that page?