| Deutsch English Français Italiano |
|
<9281c7c64154e5978fbf7bd0d90bde6b4a4a0ce9@i2pn2.org> View for Bookmarking (what is this?) Look up another Usenet article |
Path: nntp.eternal-september.org!news.eternal-september.org!eternal-september.org!feeder3.eternal-september.org!i2pn.org!i2pn2.org!.POSTED!not-for-mail From: dxf <dxforth@gmail.com> Newsgroups: comp.lang.forth Subject: Re: The future. (was Re: Parsing timestamps?) Date: Thu, 17 Jul 2025 15:55:41 +1000 Organization: i2pn2 (i2pn.org) Message-ID: <9281c7c64154e5978fbf7bd0d90bde6b4a4a0ce9@i2pn2.org> References: <1f433fabcb4d053d16cbc098dedc6c370608ac01@i2pn2.org> <nnd$0deda869$2559e613@c251414cde7edbe7> <e5d0ae0c4e16016b9aefc12737115afa@www.novabbs.com> <nnd$34fd6cd6$25a88dac@ac6bb1addf3a4136> <nnd$7cd4b038$19604994@7c17d326f65156c4> <182f3511eb7301f0aba99c9964b014c3@www.novabbs.com> <mdofu5FgnhpU1@mid.individual.net> <9a52d105667a1e2fec75d02d9f7eb9dbfbee6648@i2pn2.org> <5f2be58744bc9ce0403a0fd589c1b1a8@www.novabbs.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Thu, 17 Jul 2025 05:55:44 -0000 (UTC) Injection-Info: i2pn2.org; logging-data="979000"; mail-complaints-to="usenet@i2pn2.org"; posting-account="XPw7UV90Iy7EOhY4YuUXhpdoEf5Vz7K+BsxA/Cx8bVc"; User-Agent: Mozilla Thunderbird X-Spam-Checker-Version: SpamAssassin 4.0.0 Content-Language: en-GB In-Reply-To: <5f2be58744bc9ce0403a0fd589c1b1a8@www.novabbs.com> On 16/07/2025 6:25 pm, LIT wrote: >> It depends on how many are being programmed by the likes of GCC. >> When ATMEL hit the market the manufacturer claimed their chips >> were designed with compilers in mind. Do Arduino users program >> in hand-coded assembler? Do you? It's no longer just the chip's >> features and theoretical performance one has to worry about but >> the compilers too. > > Regarding features it's worth to mention > that ATMELs actually are quite nice to > program them in ML. Even, if they were > designed "with compilers in mind". > ... Reminds me of the 6502 for some reason. But it's the 'skip next instruction on bit in register' that throws me. Not to mention companies that release chips that don't do what the spec says. Their solution? Amend the documentation to exclude that feature! Didn't get that in the good old days as products were expected to have a reasonable lifetime. Today CPU designs are as 'throw away' as everything else. No reason to believe RISC-V will be different. Only thing distinguishing it are the years of hype and promise.