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From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: Interpreters and indirect-branch prediction
Date: Wed, 13 Nov 2024 19:36:07 +0000
Organization: Rocksolid Light
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On Wed, 13 Nov 2024 8:20:27 +0000, Anton Ertl wrote:

> mitchalsup@aol.com (MitchAlsup1) writes:
>>For something like a bytecode interpreter, the prediction accuracy
>>of the jump predictor is going to be epically bad.
>
> And with "jump predictor", you probably mean the indirect-branch
> predictor.
>
> On hardware of up to around 2005 where the indirect branches were at
> best predicted by BTBs with 2-bit counters, a "bytecode interpreter"
> with one shared indirect branch (as generated by the usual
> for...{switch...{...}} idiom in C) results in misprediction rates of
>>80% [ertl&gregg03jilp].

That certainly qualifies as bad.

>                         With one a non-shared indirect branch per VM
> instruction implementation (as in typical threaded-code
> implementations), we measured 50%-61% mispredictions for BTB with
> 2-bit counters in simulation [ertl&gregg03jilp] and similar results on
> actual CPUs.

50% misprediction rate qualifies as bad.
>
> We simulated 2-level history-based indirect branch predictors
> [ertl&gregg03jilp], and they typically have less than 10%
> mispredictions.

10% misprediction rate qualifies as "not so bad".