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From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: Why I've Dropped In
Date: Wed, 11 Jun 2025 16:37:27 +0000
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On Wed, 11 Jun 2025 9:42:47 +0000, BGB wrote:

> On 6/11/2025 12:56 AM, Thomas Koenig wrote:
>> quadibloc <quadibloc@gmail.com> schrieb:
>>
>>> Since the basis of the ISA is a RISC-like ISA,
>>
>> [...]
>>
>>> 3) Use only four base registers instead of eight.
>>> 4) Use only three index registers instead of seven.
>>> 5) Use only six index registers instead of seven, and use only four base
>>> registers instead of eight when indexing is used.
>>
>> Having different classes of base and index registers is very
>> un-RISCy, and not generally a good idea.  General purpose registers
>> is one of the great things that the /360 got right, as the VAX
>> later did, and the 68000 didn't.
>>
>
> Agreed.
>
> Ideally, one has an ISA where nearly all registers are the same:
>    No distinction between base/index/data registers;
>    No distinction between integer and floating point registers;
>    No distinction between general registers and SIMD registers;
>    ...

Agreed:: But most architectures get the FP registers wrong under that
distinction, and apparently everyone gets the SIMD registers wrong.

Maybe it should be stated:: There is one register file of k-bits per
register (where K=32, 64, 128} and that there is no distinction between
what kind of data can go in what register.

> Though, there are tradeoffs. For example, SPRs can be, by definition,
> not the same as GPRs. Say, if you have an SP or LR, almost by
> definition, you will not be using it as a GPR.

Disagree:: One uses the SP as a base register "all the time",
one uses LR as a JMP source "every subroutine return".
Either is generally done using GPRs, and thus the problem
is to guarantee that you don't have so many of them that
you can't use them naturally in your ISA>

> So, if ZR/LR/SP/GP are "not GPR", this is fine.
> Pretty much everything else is best served by being a GPR or suitably
> GPR like.
>
> ....