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From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: arm ldxr/stxr vs cas
Date: Sun, 8 Sep 2024 17:52:08 +0000
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On Sun, 8 Sep 2024 16:10:41 +0000, Scott Lurndal wrote:

> "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> writes:
>>On 9/7/2024 5:59 PM, MitchAlsup1 wrote:
>>> On Sat, 7 Sep 2024 23:16:35 +0000, Chris M. Thomasson wrote:
>
>>> Thus, it seems reasonable to fail a CAS when one cannot determine
>>> if the memory location has been changed and changed back in the
>>> mean time.
>>
>>I think Scott Lurndal mentioned something about CAS or something on
>>windows that will assert the bus lock after a lot of failures...
>
> On AMD processors (and likely intel), if a core cannot acquire
> a cache line in a a finite time, the core will assert the bus lock
> to ensure forward progress.

There are busses without the ability to LOCK (outside of x86).

> Nothing to do with the operating software;  purely a hardware thing.