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Path: ...!Xl.tags.giganews.com!local-3.nntp.ord.giganews.com!nntp.supernews.com!news.supernews.com.POSTED!not-for-mail NNTP-Posting-Date: Tue, 17 Dec 2024 20:38:18 +0000 Sender: Andrew Haley <aph@zarquon.pink> From: aph@littlepinkcloud.invalid Subject: Re: Memory ordering Newsgroups: comp.arch References: <vfono1$14l9r$1@dont-email.me> <vh4530$2mar5$1@dont-email.me> <-rKdnTO4LdoWXKj6nZ2dnZfqnPWdnZ2d@supernews.com> <vh5t5b$312cl$2@dont-email.me> <5yqdnU9eL_Y_GKv6nZ2dnZfqn_GdnZ2d@supernews.com> <2024Nov15.082512@mips.complang.tuwien.ac.at> <vh7ak1$3cm56$1@dont-email.me> <20241115152459.00004c86@yahoo.com> <vh8bn7$3j6ql$1@dont-email.me> <vhb2dc$73fe$1@dont-email.me> <vhct2q$lk1b$2@dont-email.me> <2024Nov17.161752@mips.complang.tuwien.ac.at> <vhh16e$1lp5h$1@dont-email.me> <2024Dec3.100144@mips.complang.tuwien.ac.at> <vin2rp$3ofc$1@dont-email.me> <3aa9f0a3d3dde86193abb1c01e52d03a@www.novabbs.org> <jwvser449xz.fsf-monnier+comp.arch@gnu.org> <vipv2t$v57m$1@dont-email.me> <virlki$1fhli$1@dont-email.me> <vis85o$1k2um$1@dont-email.me> <vjq76k$1aj88$1@dont-email.me> <vjrr3m$1nppo$1@dont-email.me> User-Agent: tin/1.9.2-20070201 ("Dalaruan") (UNIX) (Linux/4.18.0-553.27.1.el8_10.x86_64 (x86_64)) Message-ID: <LDSdnRp-r7KnfPz6nZ2dnZfqnPudnZ2d@supernews.com> Date: Tue, 17 Dec 2024 20:38:18 +0000 Lines: 19 X-Trace: sv3-gVr+vjYTDpfwywP+mvxPgWY4dIy4QKQgz9cgOFm9F49vNUEk5G5cnDxqGT9HO3KA8CL0GywRhE6yOre!dCF188uQgUFy0FdaroByO3zWWGd8wfvanvivXfYBz58TY6jmZ0ISL2bpM2DF0wV1swAPfMBn4XGJ!yTaxJHvj X-Complaints-To: www.supernews.com/docs/abuse.html X-DMCA-Complaints-To: www.supernews.com/docs/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 Bytes: 2548 jseigh <jseigh_es00@xemaps.com> wrote: > > C++ doesn't use #LoadStore, etc... memory ordering terminology. They > use acquire, release, cst, relaxed, ... While in some cases it's > straightforward as to what that means, in others it's less obvious. Indeed you don't know the exact mapping to instructions, but that's the idea: you ask for the ordering model you want, and the compiler chooses the instructions. > Non-obvious isn't exactly what you want when writing multi-threaded > code. There's enough subtlety as it is. There are efficiency advantages to be had from getting away from explicit barriers, though. AArch64 has seq-cst load and store instructions which don't need the sledgehammer of of a full StoreLoad between a store and a load. Andrew.