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EricP <ThatWouldBeTelling@thevillage.com> wrote:
> Michael S wrote:
>> On Thu, 27 Jun 2024 01:47:49 +0000
>> mitchalsup@aol.com (MitchAlsup1) wrote:
>> 
>>> Exactly what are you intending to mean from "single-copy atomic
>>> accesses" ??
>> 
>> It sounds as a politically correct way of saying "default memory
>> ordering of ARMv8.1-A and later".
>> I.e. weaker than x86-64 and SPARC TSO, but stronger than Itanium.
>> Probably stronger than POWER, but I am not sure if POWER ever had memory
>> ordering model formalized.
>> 
> 
> Multi-copy atomic is ARM's name for a write-update coherence protocol
> as it allows each cache to have its own copy of a single memory location.

The terminology is not Arm's, it comes from

William W. Collier. 1992. Reasoning about parallel architectures.
Prentice Hall, Englewood Cliffs.

> Single-copy atomic is their name for a write-invalidate protocol
> as it ensures that there is one value for each memory location.
> 
> Originally ARM's weak cache coherence protocol spec, like Alpha,
> did not explicitly exclude multi-copy atomic so software designers had
> to consider all the extra race conditions a write-update implementation
> might allow. But this was wasted extra effort because no one implements
> a write-update protocol, just write-invalidate.
> Eventually ARM specified that it was single-copy atomic (write-invalidate).

And it's now multi-copy atomic, thank goodness.

Andrew.