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From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: Is Intel exceptionally unsuccessful as an architecture
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Date: Sat, 21 Sep 2024 20:45:10 +0000
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On Sat, 21 Sep 2024 20:26:13 +0000, Chris M. Thomasson wrote:

> On 9/21/2024 6:54 AM, Scott Lurndal wrote:
>> mitchalsup@aol.com (MitchAlsup1) writes:
>> https://www.marvell.com/products/cxl.html
>
> What about a weak coherency where a programmer has to use the correct
> membars to get the coherency required for their specific needs? Along
> the lines of UltraSPARC in RMO mode?

In my case, I suffered through enough of these to implement a
memory hierarchy free from the need of any MemBars yet provide
the performance of <mostly> relaxed memory order, except when
certain kinds of addresses are touched {MMI/O, configuration
space, ATOMIC accesses,...} In these cases, the core becomes
{sequentially consistent, or strongly ordered} depending on the
touched address.

As far as PCIe device to device data routing, this will all be
based no the chosen virtual channel. Same channel=in order,
different channel=who knows.