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From: John Savard <quadibloc@servername.invalid>
Newsgroups: comp.arch
Subject: Re: Stealing a Great Idea from the 6600
Date: Sat, 20 Apr 2024 01:09:53 -0600
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On Fri, 19 Apr 2024 18:40:45 +0000, mitchalsup@aol.com (MitchAlsup1)
wrote:
>John Savard wrote:

>>                                        So presumably reduced ISA
>> threads will need less agressive OoO, and 1/4 the rename registers
>> might be adequate, but there's obviously no guarantee that this would
>> indeed be an ideal fit.
>
>LoL.

Well, yes. The fact that pretty much all serious high-performance
designs these days _are_ OoO basically means that my brilliant idea is
DoA.

Of course, instead of replacing 1 full-ISA thread with 4 light-ISA
threads, one could  use a different number, based on what is optimum
for a given implementation. But that ratio would now vary from one
chip to another, being model-dependent.

So it's not *totally* destroyed, but this is still a major blow.

John Savard