Path: ...!news.mixmin.net!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail
From: John Savard <quadibloc@servername.invalid>
Newsgroups: comp.arch
Subject: Re: Stealing a Great Idea from the 6600
Date: Mon, 22 Apr 2024 19:36:54 -0600
Organization: A noiseless patient Spider
Lines: 64
Message-ID: <aj3e2j13ntqoofh22cienlntgrnkgrj488@4ax.com>
References: <in312jlca131khq3vj0i24n6pb0hah2ur5@4ax.com> <71acfecad198c4e9a9b14ffab7fc1cb5@www.novabbs.org> <1s042jdli35gdo092v6uaupmrcmvo0i5vp@4ax.com> <oj742jdvpl21il2s5a1ndsp3oidsnfjmr6@4ax.com> <dd1866c4efb369b7b6cc499d718dc938@www.novabbs.org> <acq62j98dhmguil5ebce6lq4m9kkgt1fs2@4ax.com> <kkq62jppr53is4r70n151jl17bjd5kd6lv@4ax.com> <9d1fadaada2ec0683fc54688cce7cf27@www.novabbs.org> <h8gd2jduqgk7i6decn0lj902pob7bud984@4ax.com> <hmod2jpvun417k1qjm04pvro5gvt3u21rg@4ax.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Injection-Date: Tue, 23 Apr 2024 03:36:56 +0200 (CEST)
Injection-Info: dont-email.me; posting-host="7270acb597502ebace3edfa43b122dbb";
	logging-data="1458531"; mail-complaints-to="abuse@eternal-september.org";	posting-account="U2FsdGVkX18G9tQl+ELHs+lmj6DZRjBjZKUEDc0WA5k="
Cancel-Lock: sha1:S+zBCodAEVarrg7HzywIZIX3BHo=
X-Newsreader: Forte Free Agent 3.3/32.846
Bytes: 3603

On Mon, 22 Apr 2024 16:22:11 -0600, John Savard
<quadibloc@servername.invalid> wrote:

>On Mon, 22 Apr 2024 14:13:41 -0600, John Savard
><quadibloc@servername.invalid> wrote:

>>The first instruction slot:
>>
>>11111
>>00
>>(3 bits) length in instruction slots, from 2 to 7
>>(22 bits) rest of the first part of the instruction
>>
>>All remaining instruction slots:
>>
>>11111
>>(3 bits) position within instruction, from 2 to 7
>>(24 bits) rest of this part of the instruction

>The page has now been updated to reflect this modified design.

And I thought I was on to something.

The functionality - pseudo-immediates and VLIW features - was all the
same, but now everything was so much simpler. The only thing that
needed to be in a header, the three-bit field that reserved space for
pseudo-immediates, now had just three bits of overhead.

Everything else followed a normal instruction model, instead of a
complicated header.

But... if I use a header with 22 bits usable to turn instruction words
that have 22 bits available...

into instructions that are _longer_ than 32 bits...

well, guess what?

If I use half the opcode space for four-word instructions, then one
header with 22 bits available can add 7 bits to each of three
subsequent instructions.

However, 24 plus 7 is 31.

So I'm stuck at putting two instructions in three words even for a
modest extension of the instruction set...

never mind adding a whole bunch of bits for stuff like predication!

I can tease out a couple of extra bits, so that I have a 22-bit
starting word, but 26 bits in each following one, by replacing the
three bit "position" field with a field that just contains 0 in every
instruction slot but the last one, indicated with a 1.

With 26 bits, to get 33 bits - all I need for a nice expansion of the
instruction set to its "full" form - I need to add seven bits to each
one, so that now does allow one starting word to prefix three
instructions.

Still not great, but adequate. And the first word doesn't really need
a length field either, it just needs to indicate it's the first one.
Which is how I had worked something like this before.

John Savard