Path: ...!weretis.net!feeder9.news.weretis.net!i2pn.org!i2pn2.org!.POSTED!not-for-mail
From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: Tonights Tradeoff - Background Execution Buffers
Date: Wed, 9 Oct 2024 16:19:41 +0000
Organization: Rocksolid Light
Message-ID: <b7191e6ab8492ad36abb76cc966d3b0b@www.novabbs.org>
References: <vbgdms$152jq$1@dont-email.me> <vbog6d$2p2rc$1@dont-email.me> <f2d99c60ba76af28c8b63b9628fb56fa@www.novabbs.org> <vc61e6$21skv$1@dont-email.me> <vc8gl4$2m5tp$1@dont-email.me> <vcv5uj$3arh6$1@dont-email.me> <37067f65c5982e4d03825b997b23c128@www.novabbs.org> <vd352q$3s1e$1@dont-email.me> <5f8ee3d3b2321ffa7e6c570882686b57@www.novabbs.org> <vd6a5e$o0aj$2@dont-email.me> <vdnpg4$3c9e$2@dont-email.me> <2024Oct4.081931@mips.complang.tuwien.ac.at> <vdp343$9d38$1@dont-email.me> <2024Oct5.114309@mips.complang.tuwien.ac.at> <ve5mpq$2jt5k$1@dont-email.me>
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8; format=flowed
Content-Transfer-Encoding: 8bit
Injection-Info: i2pn2.org;
	logging-data="1280767"; mail-complaints-to="usenet@i2pn2.org";
	posting-account="o5SwNDfMfYu6Mv4wwLiW6e/jbA93UAdzFodw5PEa6eU";
User-Agent: Rocksolid Light
X-Spam-Checker-Version: SpamAssassin 4.0.0
X-Rslight-Site: $2y$10$cWpQkZSV1kPywMJ3Hbu3keWqmvpHW1Ifhq8Kophi5zs/1snaPV7n2
X-Rslight-Posting-User: cb29269328a20fe5719ed6a1c397e21f651bda71
Bytes: 2456
Lines: 20

On Wed, 9 Oct 2024 10:44:08 +0000, Robert Finch wrote:

>
> Been thinking some about the carry and overflow and what to do about
> register spills and reloads during expression processing. My thought was
> that on the machine with 256 registers, simply allocate a ridiculous
> number of registers for expression processing, for example 25 or even
> 50. Then if the expression is too complex, have the compiler spit out an
> error message to the programmer to simplify the expression. Remnants of
> the ‘expression too complex’ error in BASIC.

Both completely unacceptable, and in your case completely unnecessary.
in 967 subroutines I read out of My 66000 LLVM compile, I only have
3 cases of spill-fill, and that is with only 32 registers with uni-
versal constants.

Of the RISC-V code I read alongside with 32+32 registers, I counted 8.

With those statistics and 256 registers, If you can't get to essentially
0 spill=fill the problem is not with your architecture but with your
compiler.