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Path: ...!news.misty.com!weretis.net!feeder9.news.weretis.net!news.nk.ca!rocksolid2!i2pn2.org!.POSTED!not-for-mail From: mitchalsup@aol.com (MitchAlsup1) Newsgroups: comp.arch Subject: Re: a bit of history, Stealing a Great Idea from the 6600 Date: Sun, 5 May 2024 18:27:44 +0000 Organization: Rocksolid Light Message-ID: <ba0308f3cfc65d63d8610ef9a9c70d67@www.novabbs.org> References: <71acfecad198c4e9a9b14ffab7fc1cb5@www.novabbs.org> <2024May3.173347@mips.complang.tuwien.ac.at> <v139qt$121r$1@gal.iecc.com> <v151fp$15b28$1@dont-email.me> <v162bc$1623$1@gal.iecc.com> <fdfd2d7fde1050cbad7dd647f1cd991a@www.novabbs.org> <v17cq8$1o21q$1@dont-email.me> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Info: i2pn2.org; logging-data="183410"; mail-complaints-to="usenet@i2pn2.org"; posting-account="65wTazMNTleAJDh/pRqmKE7ADni/0wesT78+pyiDW8A"; User-Agent: Rocksolid Light X-Rslight-Posting-User: ac58ceb75ea22753186dae54d967fed894c3dce8 X-Spam-Checker-Version: SpamAssassin 4.0.0 X-Rslight-Site: $2y$10$wAeWrxGVLpB0RHVHTtyMP.NdS3klEETOadBh2JFeJHPh0yUMbiIoi Bytes: 2070 Lines: 18 Thomas Koenig wrote: > MitchAlsup1 <mitchalsup@aol.com> schrieb: >> (*) x86 takes craploads of cycles to cross the trap barrier and back >> {including the saving and restoration of registers} >> Something like My 66000 takes 10 each way including the saving and >> restoring of registers, and the change of MMU state. > (Maybe) stupid question: What happens to in-flight instructions on > such a trap, or an interrupt? What is the cost of that? All instructions before the trap/exception/interrupt are allowed to complete No instructions beyond the trap/exception/interrupt are allowed to complete Those instructions still in flight are allowed to proceed while the state and register file of the handler are fetched from memory. If they complete before state arrives, the overhead is zero. If they are still pending, then latency accrues from that point.