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From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: Efficiency of in-order vs. OoO
Date: Tue, 1 Oct 2024 18:45:11 +0000
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On Tue, 26 Mar 2024 14:15:41 +0000, Scott Lurndal wrote:

> anton@mips.complang.tuwien.ac.at (Anton Ertl) writes:
>>scott@slp53.sl.home (Scott Lurndal) writes:
>>>The biggest demand is from the OS vendors.    Hardware folks have
>>>simulation and emulators.
>>
>>You don't want to use a full-blown microarchitectural emulator for a
>>long-running program.
>
> Generally hardware folks don't run 'long-running programs' when
> analyzing performance, they use the emulator for determining latencies,
> bandwidths and efficiacy of cache coherency algorithms and
> cache prefetchers.
>
> Their target is not application analysis.

It is sequence compliance. At this point in the game all the FUs
are known to produce correct results. But we live in a world
where::
a) The test case takes the correct number of cycles
b) leaves all the right bit patterns in registers and memory
c) took at the right directions at all the branches
d) and went through an invalid sequence to get there.

HW verification is mostly about proving the sequencers are correct.