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From: John Savard <quadibloc@servername.invalid>
Newsgroups: comp.arch
Subject: Re: Concertlina II: Full Circle
Date: Sat, 22 Jun 2024 23:04:28 -0600
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On Wed, 19 Jun 2024 21:39:11 -0600, John Savard
<quadibloc@servername.invalid> wrote:

>So I've added operate instructions that allow operations where one
>operand is in a normal register, and the other operand is in a
>selected element of a vector register. The element is itself specified
>by the contents of an integer register, for convenient use within
>loops.
>
>Thus, a VVM-alike loop, instead of going from some vectors in memory
>to other vectors in memory, could go from some vector registers to
>other vector registers. The vectors aren't virtual any more.

Because it seemed to me that any VVM-alike instruction I had would
have to have at least an alternate form longer than 32 bits, despite
my efforts to squeeze it in to much less space than you use... I felt
that I needed to go back to an earlier iteration of Concertina for a
method of making it easier to use long instructions in programs.

Doing that, though, required me to reserve some opcode space, and one
of the consequence is that the instructions referred to above had to
be moved to an alternate instruction set!

I haven['t yet added the additional long instructions to the pages. If
I'm reserving that much opcode space (1/32nd of the total opcode
space) I'm thinking I should do something amazing with it, not
something ho-hum.

Meanwhile, though, I have added something "amazing" to the ISA for a
very tiny cost in opcode space. I've added an eleventh header type
which applies *four* prefix bits to every 16 bits in what's left of
the block after the header.

What does this do?

Well, it used to be I had 16-bit instructions occupying 1/4 of the
opcode space which included register-to-register instructions that
could involve only two registers from the same group of eight
registers.

Partly because I was told this was a very bad thing, and because I
needed to take that 1/4 of the opcode space back so I could have
load-store instructions that were not heavily restricted to squeeze
them into less space, I used prefix bits to change the 15-bit
instructions to 17-bit instructions that could use any two registers.

Well, the new header type adds the option to also, by using some
prefix bits, assign a 19-bit instruction to a 16-bit slot... and these
19-bit instructions add memory-reference instructions to the half-word
instructions.

So now, in addition to containing up to 8 ordinary 32-bit
instructions, a 256-bit block can contain up to 24 instructions
belonging to a mix of 17-bit and 19-bit instructions, short
instructions that now are a complete set, including load and store
memory reference instructions.

John Savard