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From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: ancient OS history, ARM is sort of channeling the IBM 360
Date: Sun, 30 Jun 2024 18:44:31 +0000
Organization: Rocksolid Light
Message-ID: <ca85f8bff2ea585a070f8c784e6070dc@www.novabbs.org>
References: <v5rcui$fqgj$1@dont-email.me> <memo.20240630131648.956b@jgd.cix.co.uk> <v5s173$jl70$1@dont-email.me>
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Stephen Fuld wrote:

> John Dallman wrote:
>
>> In article <v5rcui$fqgj$1@dont-email.me>, tkoenig@netcologne.de
>> (Thomas Koenig) wrote:
>>
>>> Imagine a process which resides at a certain address.  It contains
>>> code, data, and pointers to data.  Now you swap it out and want
>>> to reload it.  You can use the same base address, then everything
>>> is fine.  Or you can use a different one, where do the pointers
>>> point, especially registers which contain addresses?
>>>
>>> The /360 tried to solve this via base pointers, which all addresses
>>> were supposed calculated relative to to.  Hence the RX and RS
>>> instraction all had a base register + 12 bit offset for their
>>> addressing modes - swapping out the base registers (if you knew
>>> which ones they were, was this info in the executable?)  should have
>>> worked.  But the SS instructions for decimal arithmetic did not have
>>> base pointers, so that solution did not work in the general casse.
>>
>> And only a 12-bit offset, to boot. I've read of systems with base and
>> limit registers, where all accesses were offsets from the base (or
>> separate base registers for code and data).
>
> Yes, e.g. Univac 1108.

S.E.L 32/65 but not 32/67 or 32/87
CDC 6600 7600
CRAY-1 1/S