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From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: Byte Addressability And Beyond
Date: Sun, 5 May 2024 01:49:52 +0000
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Lawrence D'Oliveiro wrote:

> On Fri, 3 May 2024 18:42:29 -0000 (UTC), John Levine wrote:

>>>> Lawrence D'Oliveiro wrote:
>>>> 
>>>>>     move.l a, b
>>>>>     move.b b, c
>> 
>> Here's a concrete example on S/360.
>> 
>>    L    R,100
>>    STH  R,200
>> 
>> That does a four byte load of location 100 into a register, and then a
>> two byte halfword store into 200.  The load gets bytes 100 through 103
>> with 100 going into the high byte of the register.  The store puts its
>> values into bytes 200 and 201.  Since it's the low half of the
register,
>> the new contents of 200 and 201 are the old contents of 102 and 103.

> So using the same register name to address a halfword gives you the low 
> half of the register, not the high half?

> Whereas using the same memory address to address a halfword gives you the

> high half of the word at that location, not the low half?


Concrete example::

say location 100:103 contain 0xDEADBEAF

LD    R,100

R contains 0xDEADBEAF

STH   R,200

Location 200:201 contain 0XBEAF

Whereas::

LH    R,100

R contains 0xDEAD

And nobody who understands BE would even question this functionality.