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From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: My 66000 and High word facility
Date: Sat, 17 Aug 2024 20:08:55 +0000
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On Sat, 17 Aug 2024 0:24:24 +0000, Brett wrote:

> MitchAlsup1 <mitchalsup@aol.com> wrote:
>>
>> When HW is doing the saves, it does them in a known order and
>> can mark the registers "in use" or "busy" instantaneously and
>> clear that status as data arrives. When SW is doing the same,
>> SW ahs to wait for the instruction to arrive and then do them
>> one-to-small numbers at a time. HW is not so constrained.
>
> Ok, so the hardware is smart enough.

The Instructions and the compiler's use of them were co-developed.

> But has anyone told the software guys?

Use HLLs and you don't have to.

> Of course convincing programmers to RTFM is futile. ;(

Done with Instructions in HW one has to convince exactly two
people; GCC code generator and LLVM code generator.
>
> If so this is the first I have heard that more registers is not bad for
> interrupt response time.

They are also bad for pipeline stage times.

> So we are back to finding any downsides for 64 registers in My 66000.

Encoding
pipeline staging
context switch times

For example, My 66000 current encoding has room for 8 instructions
in the FMAC category (4 in use) with 6-bit register specifiers
I would need 4 major OpCodes instead of 1.

For your 98%-ile source code, 32-registers is plenty.

> Lack of actual significant benefits is irrelevant, as all the programers
> are 100% convinced that it will help some of their code. ;)
>
>> For example a 1-wide machine with a 4-ported register file,
>> generally operated as 3R1W can be switched to 4R or 4W for
>> epilogue or prologue uses respectively. Simulation indicates
>> this gets rid of 47% of the cycles spent in prologue and
>> epilogue (combined compared to a sequence of stores and loads)
>> Simulation also indicates that 42% of the power is saved--
>> mainly from Tag and TLB non-access cycles.
>>